Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 85.71 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_rd_wr_cg 85.71 1 100 1 64 64



Group Instance : i2c_rd_wr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64



Summary for Group Instance i2c_rd_wr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 2 16 88.89
Crosses 24 4 20 83.33


Variables for Group Instance i2c_rd_wr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
address_match 2 0 2 100.00 100 1 1 2
cp_address_match 4 0 4 100.00 100 1 1 0
cp_read_byte 5 1 4 80.00 100 1 1 0
cp_write_byte 5 1 4 80.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_rd_wr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_address_match_x_ip_mode 4 0 4 100.00 100 1 1 0
cross_write_byte_x_ip_mode 10 2 8 80.00 100 1 1 0
cross_read_byte_x_ip_mode 10 2 8 80.00 100 1 1 0


Summary for Variable address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for address_match

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11124286 1 T3 1385 T6 18210 T11 1154
auto[1] 15820094 1 T2 14202 T3 53 T4 19684


Summary for Variable cp_address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_address_match

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_addr_no_match 5528917 1 T3 1369 T11 1138 T12 2372
read_addr_match 11410993 1 T2 7778 T3 44 T4 12566
write_addr_no_match 5398738 1 T6 18200 T12 2653 T17 11187
write_addr_match 4294657 1 T2 6404 T4 7098 T5 264


Summary for Variable cp_read_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_read_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 3459155 1 T2 1523 T3 316 T4 2947
med 6561557 1 T2 2814 T3 431 T4 4704
low 6755457 1 T2 3326 T3 629 T4 4833
all_zero 163741 1 T2 115 T3 37 T4 82


Summary for Variable cp_write_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_write_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 1967339 1 T2 1199 T4 1438 T5 70
med 3773625 1 T2 2224 T4 2831 T5 144
low 3858358 1 T2 2908 T4 2749 T5 41
all_zero 94073 1 T2 73 T4 80 T5 9


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 11801527 1 T3 1438 T6 19478 T11 1196
host 15142853 1 T2 14202 T4 19684 T5 826


Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins
address_matchip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] device 11124159 1 T3 1385 T6 18210 T11 1154
auto[0] host 127 1 T83 21 T122 6 T123 2
auto[1] device 677368 1 T3 53 T6 1268 T11 42
auto[1] host 15142726 1 T2 14202 T4 19684 T5 826


Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1153302 1 T6 3719 T12 856 T17 2339
high host 814037 1 T2 1199 T4 1438 T5 70
med device 2197925 1 T6 7645 T12 849 T17 4248
med host 1575700 1 T2 2224 T4 2831 T5 144
low device 2283152 1 T6 7922 T12 1002 T17 4893
low host 1575206 1 T2 2908 T4 2749 T5 41
all_zero device 53950 1 T6 164 T12 42 T17 54
all_zero host 40123 1 T2 73 T4 80 T5 9


Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1153302 1 T6 3719 T12 856 T17 2339
high host 814037 1 T2 1199 T4 1438 T5 70
med device 2197925 1 T6 7645 T12 849 T17 4248
med host 1575700 1 T2 2224 T4 2831 T5 144
low device 2283152 1 T6 7922 T12 1002 T17 4893
low host 1575206 1 T2 2908 T4 2749 T5 41
all_zero device 53950 1 T6 164 T12 42 T17 54
all_zero host 40123 1 T2 73 T4 80 T5 9

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