Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50415001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11328466

1

T1

1

T2

2308

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	60669667	1			T1	1		T2	15159		T3	69
values[0x0]	535903	1			T2	416		T3	31		T4	167
values[0x1]	537897	1			T2	362		T3	42		T4	182

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35936139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25807328

1

T1

1

T2

6644

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	217787	1			T4	80		T5	6		T6	6
valid_sources[0x01]	272546	1			T4	56		T5	3		T6	10
valid_sources[0x02]	261801	1			T4	73		T5	3		T6	6
valid_sources[0x03]	217811	1			T4	60		T5	7		T6	8
valid_sources[0x04]	244509	1			T4	40		T5	6		T6	3
valid_sources[0x05]	229148	1			T4	68		T5	1		T6	3
valid_sources[0x06]	217408	1			T4	40		T5	5		T6	8
valid_sources[0x07]	260172	1			T4	53		T5	4		T6	6
valid_sources[0x08]	210872	1			T3	138		T4	59		T5	1
valid_sources[0x09]	216981	1			T4	92		T5	2		T6	2
valid_sources[0x0a]	236748	1			T4	52		T5	3		T6	5
valid_sources[0x0b]	332876	1			T4	60		T5	6		T6	6
valid_sources[0x0c]	207096	1			T4	56		T5	2		T6	4
valid_sources[0x0d]	234308	1			T4	65		T6	6		T7	104
valid_sources[0x0e]	227534	1			T4	80		T5	4		T6	8
valid_sources[0x0f]	222056	1			T4	63		T5	1		T6	5
valid_sources[0x10]	223790	1			T4	48		T5	9		T6	6
valid_sources[0x11]	221170	1			T4	60		T5	8		T6	5
valid_sources[0x12]	215434	1			T4	74		T5	2		T6	1
valid_sources[0x13]	239902	1			T4	59		T5	1		T6	5
valid_sources[0x14]	212677	1			T4	65		T5	1		T6	8
valid_sources[0x15]	213519	1			T4	69		T5	4		T6	1
valid_sources[0x16]	232530	1			T4	67		T5	6		T6	4
valid_sources[0x17]	223463	1			T4	59		T5	2		T6	5
valid_sources[0x18]	228208	1			T4	65		T5	5		T6	6
valid_sources[0x19]	243472	1			T2	96		T4	63		T5	2
valid_sources[0x1a]	227436	1			T4	45		T5	2		T6	4
valid_sources[0x1b]	240441	1			T4	60		T5	5		T6	2
valid_sources[0x1c]	389567	1			T4	61		T5	4		T6	4
valid_sources[0x1d]	214951	1			T4	63		T5	2		T6	5
valid_sources[0x1e]	208365	1			T4	51		T5	3		T6	5
valid_sources[0x1f]	227121	1			T4	45		T5	8		T6	10
valid_sources[0x20]	217203	1			T2	95		T4	62		T5	3
valid_sources[0x21]	218721	1			T4	75		T5	2		T6	5
valid_sources[0x22]	222622	1			T4	52		T5	5		T6	4
valid_sources[0x23]	227024	1			T4	69		T5	2		T6	5
valid_sources[0x24]	255305	1			T4	62		T5	3		T6	10
valid_sources[0x25]	218590	1			T4	67		T5	3		T6	8
valid_sources[0x26]	211057	1			T4	58		T5	4		T6	5
valid_sources[0x27]	231541	1			T4	74		T5	4		T6	5
valid_sources[0x28]	217932	1			T4	62		T5	3		T6	5
valid_sources[0x29]	237248	1			T4	48		T5	6		T6	6
valid_sources[0x2a]	206556	1			T4	65		T6	8		T7	140
valid_sources[0x2b]	232437	1			T4	62		T5	9		T6	8
valid_sources[0x2c]	292540	1			T4	85		T6	8		T7	168
valid_sources[0x2d]	246884	1			T4	54		T5	6		T6	6
valid_sources[0x2e]	226668	1			T2	204		T4	56		T5	4
valid_sources[0x2f]	220388	1			T4	50		T5	4		T6	6
valid_sources[0x30]	224487	1			T4	53		T5	1		T6	10
valid_sources[0x31]	223763	1			T4	73		T5	5		T6	3
valid_sources[0x32]	210985	1			T4	78		T5	2		T6	9
valid_sources[0x33]	213795	1			T2	153		T4	56		T5	2
valid_sources[0x34]	219030	1			T2	211		T4	73		T5	5
valid_sources[0x35]	253975	1			T4	53		T5	4		T6	9
valid_sources[0x36]	254302	1			T4	58		T5	4		T6	4
valid_sources[0x37]	238967	1			T4	63		T5	3		T6	5
valid_sources[0x38]	229069	1			T2	158		T4	70		T5	1
valid_sources[0x39]	210032	1			T4	59		T5	3		T6	5
valid_sources[0x3a]	222219	1			T2	755		T4	62		T5	1
valid_sources[0x3b]	261747	1			T4	63		T5	4		T6	4
valid_sources[0x3c]	316037	1			T4	55		T5	3		T6	8
valid_sources[0x3d]	224808	1			T4	53		T5	5		T6	5
valid_sources[0x3e]	246731	1			T4	70		T5	6		T6	8
valid_sources[0x3f]	217089	1			T4	77		T5	6		T6	5
valid_sources[0x40]	239427	1			T4	57		T5	2		T6	9
valid_sources[0x41]	207696	1			T4	72		T5	4		T6	8
valid_sources[0x42]	278579	1			T4	59		T5	5		T6	3
valid_sources[0x43]	342214	1			T4	71		T5	2		T6	4
valid_sources[0x44]	254218	1			T4	59		T5	3		T6	4
valid_sources[0x45]	238173	1			T4	71		T5	7		T6	4
valid_sources[0x46]	212706	1			T2	936		T4	67		T5	4
valid_sources[0x47]	253451	1			T4	61		T5	1		T6	6
valid_sources[0x48]	242344	1			T4	64		T5	1		T6	6
valid_sources[0x49]	219140	1			T4	61		T5	7		T6	4
valid_sources[0x4a]	335904	1			T4	56		T5	2		T6	2
valid_sources[0x4b]	211883	1			T4	55		T5	6		T6	6
valid_sources[0x4c]	216145	1			T4	66		T5	2		T6	3
valid_sources[0x4d]	232687	1			T4	71		T5	8		T6	9
valid_sources[0x4e]	325956	1			T2	710		T4	61		T5	1
valid_sources[0x4f]	250583	1			T4	54		T5	3		T6	4
valid_sources[0x50]	221864	1			T4	53		T5	4		T6	8
valid_sources[0x51]	316225	1			T2	481		T4	55		T5	3
valid_sources[0x52]	220110	1			T4	48		T5	3		T6	5
valid_sources[0x53]	238703	1			T4	57		T5	3		T6	9
valid_sources[0x54]	235369	1			T4	55		T5	3		T6	4
valid_sources[0x55]	212621	1			T4	56		T5	4		T6	3
valid_sources[0x56]	232351	1			T2	850		T4	48		T5	8
valid_sources[0x57]	232111	1			T4	60		T5	3		T6	7
valid_sources[0x58]	216001	1			T4	67		T5	2		T6	7
valid_sources[0x59]	245167	1			T4	70		T5	9		T6	6
valid_sources[0x5a]	313599	1			T4	47		T5	2		T6	5
valid_sources[0x5b]	226673	1			T4	74		T5	1		T6	1
valid_sources[0x5c]	230030	1			T1	1		T4	65		T5	6
valid_sources[0x5d]	225269	1			T2	373		T4	65		T5	1
valid_sources[0x5e]	233522	1			T4	73		T5	5		T6	4
valid_sources[0x5f]	232924	1			T4	53		T5	3		T6	9
valid_sources[0x60]	279889	1			T4	51		T5	5		T6	9
valid_sources[0x61]	217228	1			T4	64		T5	2		T6	7
valid_sources[0x62]	210697	1			T4	65		T5	3		T6	7
valid_sources[0x63]	235519	1			T4	48		T5	2		T6	2
valid_sources[0x64]	213358	1			T4	68		T5	4		T6	6
valid_sources[0x65]	216865	1			T4	65		T5	5		T6	5
valid_sources[0x66]	230354	1			T4	57		T5	2		T6	4
valid_sources[0x67]	207222	1			T4	56		T5	2		T6	9
valid_sources[0x68]	221373	1			T4	68		T5	3		T6	6
valid_sources[0x69]	213012	1			T4	52		T5	6		T6	2
valid_sources[0x6a]	228488	1			T2	492		T4	63		T5	3
valid_sources[0x6b]	234527	1			T4	51		T5	4		T6	11
valid_sources[0x6c]	227556	1			T4	41		T6	2		T7	145
valid_sources[0x6d]	223099	1			T4	71		T5	1		T6	2
valid_sources[0x6e]	222745	1			T2	87		T4	74		T5	3
valid_sources[0x6f]	232779	1			T4	65		T5	4		T6	9
valid_sources[0x70]	223385	1			T4	55		T5	2		T6	8
valid_sources[0x71]	233782	1			T2	1478		T4	54		T5	3
valid_sources[0x72]	220132	1			T4	70		T6	3		T7	97
valid_sources[0x73]	222292	1			T4	71		T5	2		T6	6
valid_sources[0x74]	217886	1			T4	68		T5	2		T6	7
valid_sources[0x75]	227979	1			T2	746		T4	62		T5	2
valid_sources[0x76]	347408	1			T4	60		T5	1		T6	3
valid_sources[0x77]	216741	1			T4	73		T5	3		T6	3
valid_sources[0x78]	250658	1			T4	64		T5	2		T6	9
valid_sources[0x79]	242760	1			T4	77		T5	1		T6	9
valid_sources[0x7a]	208304	1			T4	54		T5	2		T6	9
valid_sources[0x7b]	217076	1			T4	49		T5	4		T6	4
valid_sources[0x7c]	220697	1			T4	81		T5	8		T6	7
valid_sources[0x7d]	239997	1			T4	69		T5	1		T6	3
valid_sources[0x7e]	228446	1			T4	51		T5	1		T6	5
valid_sources[0x7f]	230144	1			T4	70		T5	3		T6	3
valid_sources[0x80]	325803	1			T2	2277		T4	66		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10872120

1

T1

1

T2

1822

T3

4

values[0x0]

all_enables

biggest_size

270683

1

T2

283

T3

10

T4

87

values[0x1]

all_enables

biggest_size

185663

1

T2

203

T3

14

T4

66