Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	96.08	100.00	84.31			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.70	100.00	84.28			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
96.08	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T33,T34
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T42,T68
1	1	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T10,T13,T42

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T10,T13,T42
1	Covered	T2,T3,T4

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T42
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T4,T7,T10

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T3,T4
1	0	-	Covered	T2,T3,T4
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	5924	5924	0	0
MinimalSramFifoDepth_A	5924	5924	0	0
NoErr_A	1945082892	1944356068	0	0
NoSramReadWhenEmpty_A	1945082892	1566747178	0	0
NoSramWriteWhenFull_A	1945082892	32875980	0	0
OupBufWreadyAfterSramRead_A	1945082892	653120	0	0
SramRvalidAfterRead_A	1945082892	653120	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5924	5924	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5924	5924	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945082892	1944356068	0	0
T1	15808	12420	0	0
T2	454060	453768	0	0
T3	62424	62036	0	0
T4	567012	566628	0	0
T5	46456	46068	0	0
T6	2048724	2048696	0	0
T7	805120	804852	0	0
T8	142660	142280	0	0
T9	266540	266292	0	0
T10	530412	530072	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945082892	1566747178	0	0
T1	15808	12420	0	0
T2	454060	411771	0	0
T3	62424	49170	0	0
T4	567012	472945	0	0
T5	46456	40443	0	0
T6	2048724	1552914	0	0
T7	805120	617243	0	0
T8	142660	118998	0	0
T9	266540	242451	0	0
T10	530412	462411	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945082892	32875980	0	0
T4	283506	21535	0	0
T5	23228	0	0	0
T6	1024362	0	0	0
T7	402560	3285	0	0
T8	71330	0	0	0
T9	133270	0	0	0
T10	265206	4616	0	0
T15	196971	23	0	0
T16	0	17	0	0
T17	509512	3412	0	0
T27	0	4081	0	0
T28	0	66210	0	0
T31	232986	41495	0	0
T32	22116	0	0	0
T33	0	17644	0	0
T34	0	24683	0	0
T42	0	73413	0	0
T43	0	22458	0	0
T79	5788	0	0	0
T81	0	481	0	0
T93	0	565	0	0
T103	0	2808	0	0
T105	0	6775	0	0
T128	0	11616	0	0
T129	0	40	0	0
T130	0	27722	0	0
T131	0	3844	0	0
T132	188721	0	0	0
T133	187631	0	0	0
T134	9899	0	0	0
T135	69748	0	0	0
T136	960	0	0	0
T137	490936	0	0	0
T138	410648	0	0	0
T139	25621	0	0	0
T140	21912	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945082892	653120	0	0
T2	113515	224	0	0
T3	31212	0	0	0
T4	425259	366	0	0
T5	34842	13	0	0
T6	2048724	699	0	0
T7	805120	930	0	0
T8	142660	108	0	0
T9	266540	120	0	0
T10	530412	151	0	0
T11	12108	0	0	0
T12	0	62	0	0
T13	0	172	0	0
T14	0	269	0	0
T17	0	245	0	0
T18	0	736	0	0
T19	0	780	0	0
T27	0	263	0	0
T29	0	152	0	0
T31	465972	1026	0	0
T32	33174	0	0	0
T38	0	15	0	0
T61	48988	213	0	0
T79	5788	0	0	0
T80	0	181	0	0
T81	0	1625	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945082892	653120	0	0
T2	113515	224	0	0
T3	31212	0	0	0
T4	425259	366	0	0
T5	34842	13	0	0
T6	2048724	699	0	0
T7	805120	930	0	0
T8	142660	108	0	0
T9	266540	120	0	0
T10	530412	151	0	0
T11	12108	0	0	0
T12	0	62	0	0
T13	0	172	0	0
T14	0	269	0	0
T17	0	245	0	0
T18	0	736	0	0
T19	0	780	0	0
T27	0	263	0	0
T29	0	152	0	0
T31	465972	1026	0	0
T32	33174	0	0	0
T38	0	15	0	0
T61	48988	213	0	0
T79	5788	0	0	0
T80	0	181	0	0
T81	0	1625	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T12

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T71,T72
1	1	Covered	T3,T11,T12

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T11,T12

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T11,T12

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T11,T12

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T27,T28
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T27,T28

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Not Covered
1	1	Covered	T17,T27,T28

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T11,T12
1	0	-	Covered	T3,T11,T12
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1481	1481	0	0
MinimalSramFifoDepth_A	1481	1481	0	0
NoErr_A	486270723	486089017	0	0
NoSramReadWhenEmpty_A	486270723	431648997	0	0
NoSramWriteWhenFull_A	486270723	3593527	0	0
OupBufWreadyAfterSramRead_A	486270723	163384	0	0
SramRvalidAfterRead_A	486270723	163384	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	486089017	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	431648997	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	2643	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	3593527	0	0
T13	0	4840	0	0
T17	509512	3412	0	0
T18	145143	0	0	0
T27	496247	4081	0	0
T28	91256	66210	0	0
T30	0	2233	0	0
T38	27023	0	0	0
T39	21780	0	0	0
T44	8090	0	0	0
T51	15754	0	0	0
T80	109686	0	0	0
T81	354591	0	0	0
T141	0	47791	0	0
T142	0	494	0	0
T143	0	212	0	0
T144	0	2517	0	0
T145	0	63717	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	163384	0	0
T3	15606	51	0	0
T4	141753	0	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	0	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	0	0	0
T11	0	40	0	0
T12	0	83	0	0
T13	0	927	0	0
T14	0	230	0	0
T17	0	995	0	0
T27	0	1130	0	0
T28	0	258	0	0
T29	0	49	0	0
T30	0	214	0	0
T31	116493	0	0	0
T32	11058	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	163384	0	0
T3	15606	51	0	0
T4	141753	0	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	0	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	0	0	0
T11	0	40	0	0
T12	0	83	0	0
T13	0	927	0	0
T14	0	230	0	0
T17	0	995	0	0
T27	0	1130	0	0
T28	0	258	0	0
T29	0	49	0	0
T30	0	214	0	0
T31	116493	0	0	0
T32	11058	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T68,T49
1	1	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T10,T68,T49

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T10,T68,T49
1	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T68,T49
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T31
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T31

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T4,T10,T31

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T4,T5
1	0	-	Covered	T2,T4,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1481	1481	0	0
MinimalSramFifoDepth_A	1481	1481	0	0
NoErr_A	486270723	486089017	0	0
NoSramReadWhenEmpty_A	486270723	411221751	0	0
NoSramWriteWhenFull_A	486270723	28498206	0	0
OupBufWreadyAfterSramRead_A	486270723	161203	0	0
SramRvalidAfterRead_A	486270723	161203	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	486089017	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	411221751	0	0
T1	3952	3105	0	0
T2	113515	71445	0	0
T3	15606	15509	0	0
T4	141753	65681	0	0
T5	11614	5892	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	12288	0	0
T9	66635	42732	0	0
T10	132603	76030	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	28498206	0	0
T4	141753	21476	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	0	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	4606	0	0
T31	116493	41412	0	0
T32	11058	0	0	0
T42	0	72699	0	0
T43	0	22458	0	0
T79	2894	0	0	0
T105	0	6775	0	0
T128	0	11616	0	0
T129	0	40	0	0
T130	0	27722	0	0
T131	0	3844	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	161203	0	0
T2	113515	224	0	0
T3	15606	0	0	0
T4	141753	287	0	0
T5	11614	13	0	0
T6	512181	0	0	0
T7	201280	0	0	0
T8	35665	108	0	0
T9	66635	120	0	0
T10	132603	89	0	0
T31	116493	860	0	0
T38	0	15	0	0
T61	0	213	0	0
T81	0	819	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	161203	0	0
T2	113515	224	0	0
T3	15606	0	0	0
T4	141753	287	0	0
T5	11614	13	0	0
T6	512181	0	0	0
T7	201280	0	0	0
T8	35665	108	0	0
T9	66635	120	0	0
T10	132603	89	0	0
T31	116493	860	0	0
T38	0	15	0	0
T61	0	213	0	0
T81	0	819	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16
1	1	Covered	T3,T6,T11

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T6,T12,T17

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T17
0	1	Covered	T6,T12,T17
1	0	Covered	T13,T143,T146

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T13,T143,T146
1	Covered	T6,T12,T17

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T13,T143,T146
0	1	Covered	T6,T12,T17
1	0	Covered	T6,T12,T17

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T12,T17
1	1	Covered	T6,T12,T17

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T12,T17
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T12,T17

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T12,T17

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Not Covered
1	1	Covered	T15,T16

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6,T12,T17
1	0	-	Covered	T6,T12,T17
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1481	1481	0	0
MinimalSramFifoDepth_A	1481	1481	0	0
NoErr_A	486270723	486089017	0	0
NoSramReadWhenEmpty_A	486270723	272804234	0	0
NoSramWriteWhenFull_A	486270723	40	0	0
OupBufWreadyAfterSramRead_A	486270723	155994	0	0
SramRvalidAfterRead_A	486270723	155994	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	486089017	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	272804234	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	16392	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	40	0	0
T15	196971	23	0	0
T16	0	17	0	0
T132	188721	0	0	0
T133	187631	0	0	0
T134	9899	0	0	0
T135	69748	0	0	0
T136	960	0	0	0
T137	490936	0	0	0
T138	410648	0	0	0
T139	25621	0	0	0
T140	21912	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	155994	0	0
T6	512181	699	0	0
T7	201280	0	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	0	0	0
T11	12108	0	0	0
T12	0	62	0	0
T13	0	172	0	0
T14	0	269	0	0
T17	0	245	0	0
T18	0	736	0	0
T19	0	780	0	0
T27	0	263	0	0
T29	0	152	0	0
T31	116493	0	0	0
T32	11058	0	0	0
T61	48988	0	0	0
T79	2894	0	0	0
T80	0	181	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	155994	0	0
T6	512181	699	0	0
T7	201280	0	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	0	0	0
T11	12108	0	0	0
T12	0	62	0	0
T13	0	172	0	0
T14	0	269	0	0
T17	0	245	0	0
T18	0	736	0	0
T19	0	780	0	0
T27	0	263	0	0
T29	0	152	0	0
T31	116493	0	0	0
T32	11058	0	0	0
T61	48988	0	0	0
T79	2894	0	0	0
T80	0	181	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T33,T34
1	1	Covered	T2,T4,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T42,T69,T70
1	1	Covered	T4,T7,T10

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T10
0	1	Covered	T4,T7,T10
1	0	Covered	T42,T69,T70

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T42,T69,T70
1	Covered	T4,T7,T10

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T42,T69,T70
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T10

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T10

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Not Covered
1	1	Covered	T4,T7,T10

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T7,T10
1	0	-	Covered	T4,T7,T10
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1481	1481	0	0
MinimalSramFifoDepth_A	1481	1481	0	0
NoErr_A	486270723	486089017	0	0
NoSramReadWhenEmpty_A	486270723	451072196	0	0
NoSramWriteWhenFull_A	486270723	784207	0	0
OupBufWreadyAfterSramRead_A	486270723	172539	0	0
SramRvalidAfterRead_A	486270723	172539	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	486089017	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	141657	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	201213	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	132518	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	451072196	0	0
T1	3952	3105	0	0
T2	113515	113442	0	0
T3	15606	15509	0	0
T4	141753	123950	0	0
T5	11614	11517	0	0
T6	512181	512174	0	0
T7	201280	13604	0	0
T8	35665	35570	0	0
T9	66635	66573	0	0
T10	132603	121345	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	784207	0	0
T4	141753	59	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	3285	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	10	0	0
T31	116493	83	0	0
T32	11058	0	0	0
T33	0	17644	0	0
T34	0	24683	0	0
T42	0	714	0	0
T79	2894	0	0	0
T81	0	481	0	0
T93	0	565	0	0
T103	0	2808	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	172539	0	0
T4	141753	79	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	930	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	62	0	0
T31	116493	166	0	0
T32	11058	0	0	0
T42	0	1312	0	0
T79	2894	0	0	0
T81	0	806	0	0
T93	0	682	0	0
T103	0	868	0	0
T128	0	80	0	0
T129	0	992	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486270723	172539	0	0
T4	141753	79	0	0
T5	11614	0	0	0
T6	512181	0	0	0
T7	201280	930	0	0
T8	35665	0	0	0
T9	66635	0	0	0
T10	132603	62	0	0
T31	116493	166	0	0
T32	11058	0	0	0
T42	0	1312	0	0
T79	2894	0	0	0
T81	0	806	0	0
T93	0	682	0	0
T103	0	868	0	0
T128	0	80	0	0
T129	0	992	0	0