Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.38	97.74	78.46			93.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	92.38	97.74	78.46			93.33	100.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.38	97.74	78.46			93.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.58	94.99	84.60		68.45	90.15	94.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_acq_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_cmd_complete	100.00	100.00	100.00			100.00	100.00
intr_hw_controller_halt	100.00	100.00	100.00			100.00	100.00
intr_hw_fmt_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_host_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_scl_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_unstable	100.00	100.00	100.00			100.00	100.00
intr_hw_stretch_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_stretch	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_unexp_stop	100.00	100.00	100.00			100.00	100.00
u_fifos	94.57	99.86	86.27			98.65	93.48
u_i2c_bus_monitor	89.50	96.26	90.32		81.82	89.58
u_i2c_controller_fsm	83.98	90.80	76.64		66.67	85.79	100.00
u_i2c_sync_scl	100.00	100.00				100.00
u_i2c_sync_sda	100.00	100.00				100.00
u_i2c_target_fsm	80.92	86.76	74.17		67.92	75.76	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		133	130	97.74
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
ALWAYS	262	5	5	100.00
ALWAYS	274	5	5	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	364	1	0	0.00
CONT_ASSIGN	365	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	367	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
ALWAYS	459	5	5	100.00
ALWAYS	469	6	6	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	871	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
237	1	1
238	1	1
240	1	1
242	1	1
243	1	1
245	1	1
246	1	1
247	1	1
249	1	1
253	1	1
255	1	1
256	1	1
257	1	1
258	1	1
262	1	1
263	1	1
264	1	1
267	1	1
268	1	1
274	1	1
275	1	1
276	1	1
278	1	1
279	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
296	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
306	1	1
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
313	1	1
314	1	1
317	1	1
319	1	1
321	1	1
323	1	1
325	1	1
326	1	1
331	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
349	1	1
358	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	0	1
365	0	1
366	0	1
367	1	1
368	1	1
412	1	1
417	1	1
419	1	1
422	1	1
423	1	1
428	1	1
455	1	1
456	1	1
459	1	1
460	1	1
461	1	1
463	1	1
464	1	1
469	1	1
470	1	1
471	1	1
480	1	1
481	1	1
482	1	1
			MISSING_ELSE
485	1	1
486	1	1
488	1	1
489	1	1
491	1	1
850	1	1
852	1	1
854	1	1
856	1	1
857	1	1
865	1	1
868	1	1
870	1	1
871	1	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	130	102	78.46
Logical	130	102	78.46
Non-Logical	0	0
Event	0	0

 LINE       237
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       242
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T79,T66,T82

 LINE       243
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T79,T66,T82

 LINE       249
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T2,T4,T5

 LINE       253
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T11
1	1	Not Covered

 LINE       267
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T3,T6,T11
1	1	Covered	T1,T2,T3

 LINE       268
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T3,T6,T11
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
             ------------1-----------    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       294
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
                -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
             ------------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       296
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T12,T13,T14
1	1	Not Covered

 LINE       306
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T27,T51
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       307
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T27,T51
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       311
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T33
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       312
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T27,T51
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       325
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T7,T33,T34

 LINE       326
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T6,T18,T19

 LINE       331
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Covered	T2,T4,T5

 LINE       344
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       345
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       346
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       347
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       348
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       349
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       419
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T11
1	1	Covered	T3,T6,T11

 LINE       419
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       422
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       423
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       428
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T6,T11

 LINE       428
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T11

 LINE       428
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T27,T28
1	0	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T11

 LINE       455
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T3,T6,T11
1	1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T3,T6,T11
1	1	Covered	T1,T2,T3

 LINE       471
 EXPRESSION ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q))
             -----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       471
 SUB-EXPRESSION (scl_fsm != scl_fsm_q)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       471
 SUB-EXPRESSION (sda_fsm != sda_fsm_q)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       481
 EXPRESSION (bus_event_detect_cnt != '0)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       485
 EXPRESSION (bus_event_detect_cnt == '0)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       486
 EXPRESSION (bus_event_detect && scl_sync && (sda_fsm_q != sda_sync))
             --------1-------    ----2---    -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       486
 SUB-EXPRESSION (sda_fsm_q != sda_sync)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       488
 EXPRESSION (controller_transmitting && sda_released_but_low)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T31,T32,T38

 LINE       489
 EXPRESSION (target_transmitting && sda_released_but_low)
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T6,T11
1	1	Not Covered

 LINE       854
 EXPRESSION (event_bus_active_timeout && ((!host_idle)))
             ------------1-----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       865
 EXPRESSION (event_read_cmd_received && reg2hw.ctrl.tx_stretch_ctrl_en.q)
             -----------1-----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T3,T11,T12
1	1	Covered	T20,T21,T22

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		30	28	93.33
TERNARY	242	2	2	100.00
TERNARY	243	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	345	2	2	100.00
TERNARY	346	2	2	100.00
TERNARY	347	2	2	100.00
TERNARY	348	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	422	2	1	50.00
TERNARY	423	2	1	50.00
IF	262	2	2	100.00
IF	274	2	2	100.00
IF	459	2	2	100.00
IF	469	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	242	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T79,T66,T82
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T79,T66,T82
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	345	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	348	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	422	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	459	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((!rst_ni))
-2-:	471	if (((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q)))
-3-:	481	if ((bus_event_detect_cnt != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T2,T3,T4

---

Assert Coverage for Module : i2c_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqFifoDepthValid_A	1481	1481	0	0
FifoDepthValid_A	1481	1481	0	0

AcqFifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

FifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0