Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	487588316	0	0	0
ctrl_rd_A	487588316	1720	0	0
host_fifo_config_rd_A	487588316	4337	0	0
host_nack_handler_timeout_rd_A	487588316	1212	0	0
host_timeout_ctrl_rd_A	487588316	1041	0	0
intr_enable_rd_A	487588316	2441	0	0
ovrd_rd_A	487588316	1712	0	0
target_fifo_config_rd_A	487588316	1166	0	0
target_id_rd_A	487588316	1423	0	0
target_timeout_ctrl_rd_A	487588316	1052	0	0
timeout_ctrl_rd_A	487588316	1056	0	0
timing0_rd_A	487588316	1139	0	0
timing1_rd_A	487588316	1191	0	0
timing2_rd_A	487588316	1241	0	0
timing3_rd_A	487588316	1251	0	0
timing4_rd_A	487588316	1199	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1720	0	0
T83	673675	19	0	0
T84	5871	35	0	0
T85	3179	29	0	0
T86	6406	24	0	0
T87	2338	29	0	0
T88	2203	10	0	0
T89	4590	3	0	0
T90	8610	3	0	0
T91	14444	244	0	0
T92	6065	23	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	4337	0	0
T30	84779	0	0	0
T36	123650	0	0	0
T40	9991	0	0	0
T42	124533	0	0	0
T45	7782	0	0	0
T53	13569	0	0	0
T93	312831	124	0	0
T94	0	138	0	0
T95	0	123	0	0
T96	0	163	0	0
T97	0	131	0	0
T98	0	169	0	0
T99	0	280	0	0
T100	0	58	0	0
T101	0	152	0	0
T102	0	186	0	0
T103	184057	0	0	0
T104	120793	0	0	0
T105	22861	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1212	0	0
T83	673675	9	0	0
T84	5871	3	0	0
T86	6406	54	0	0
T87	2338	4	0	0
T88	2203	8	0	0
T89	4590	5	0	0
T90	8610	1	0	0
T91	14444	237	0	0
T106	5624	9	0	0
T107	8704	47	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1041	0	0
T83	673675	2	0	0
T84	5871	22	0	0
T85	3179	4	0	0
T86	6406	64	0	0
T87	2338	3	0	0
T88	2203	7	0	0
T89	4590	10	0	0
T90	8610	15	0	0
T91	14444	228	0	0
T92	6065	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	2441	0	0
T11	12108	0	0	0
T12	33596	0	0	0
T17	509512	0	0	0
T31	116493	4	0	0
T32	11058	0	0	0
T38	27023	0	0	0
T56	0	3	0	0
T61	48988	0	0	0
T79	2894	0	0	0
T80	109686	0	0	0
T81	354591	0	0	0
T83	0	130	0	0
T102	0	42	0	0
T108	0	33	0	0
T109	0	11	0	0
T110	0	22	0	0
T111	0	13	0	0
T112	0	22	0	0
T113	0	2	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1712	0	0
T11	12108	0	0	0
T12	33596	0	0	0
T17	509512	0	0	0
T27	496247	0	0	0
T38	27023	0	0	0
T39	21780	0	0	0
T61	48988	0	0	0
T66	0	67	0	0
T79	2894	71	0	0
T80	109686	0	0	0
T81	354591	0	0	0
T83	0	12	0	0
T114	0	40	0	0
T115	0	20	0	0
T116	0	56	0	0
T117	0	47	0	0
T118	0	37	0	0
T119	0	57	0	0
T120	0	31	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1166	0	0
T83	673675	14	0	0
T84	5871	34	0	0
T85	3179	7	0	0
T86	6406	49	0	0
T87	2338	1	0	0
T88	2203	4	0	0
T89	4590	6	0	0
T90	8610	14	0	0
T91	14444	239	0	0
T92	6065	17	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1423	0	0
T83	673675	4	0	0
T84	5871	79	0	0
T85	3179	7	0	0
T86	6406	13	0	0
T87	2338	5	0	0
T88	2203	1	0	0
T89	4590	4	0	0
T90	8610	6	0	0
T91	14444	212	0	0
T92	6065	15	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1052	0	0
T83	673675	10	0	0
T84	5871	39	0	0
T85	3179	3	0	0
T86	6406	25	0	0
T87	2338	4	0	0
T88	2203	6	0	0
T89	4590	8	0	0
T91	14444	210	0	0
T92	6065	33	0	0
T121	1805	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1056	0	0
T83	673675	11	0	0
T84	5871	40	0	0
T85	3179	4	0	0
T86	6406	17	0	0
T87	2338	3	0	0
T88	2203	6	0	0
T89	4590	5	0	0
T90	8610	16	0	0
T91	14444	202	0	0
T92	6065	13	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1139	0	0
T83	673675	24	0	0
T84	5871	44	0	0
T85	3179	8	0	0
T86	6406	14	0	0
T87	2338	12	0	0
T88	2203	10	0	0
T89	4590	5	0	0
T90	8610	12	0	0
T91	14444	243	0	0
T92	6065	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1191	0	0
T83	673675	11	0	0
T84	5871	38	0	0
T85	3179	27	0	0
T86	6406	46	0	0
T87	2338	5	0	0
T88	2203	8	0	0
T89	4590	5	0	0
T90	8610	36	0	0
T91	14444	236	0	0
T92	6065	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1241	0	0
T83	673675	7	0	0
T84	5871	59	0	0
T86	6406	50	0	0
T87	2338	6	0	0
T88	2203	6	0	0
T89	4590	3	0	0
T90	8610	8	0	0
T91	14444	255	0	0
T92	6065	24	0	0
T106	5624	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1251	0	0
T83	673675	8	0	0
T84	5871	50	0	0
T85	3179	1	0	0
T86	6406	48	0	0
T87	2338	3	0	0
T88	2203	5	0	0
T89	4590	4	0	0
T90	8610	16	0	0
T91	14444	242	0	0
T92	6065	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487588316	1199	0	0
T83	673675	10	0	0
T84	5871	27	0	0
T85	3179	23	0	0
T86	6406	87	0	0
T87	2338	2	0	0
T88	2203	1	0	0
T89	4590	9	0	0
T91	14444	207	0	0
T92	6065	16	0	0
T121	1805	6	0	0