SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
0.00 | 0.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.status_cg | 0.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 20 | 20 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acqempty | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_acqfull | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_fmtempty | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_fmtfull | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_hostidle | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_rxempty | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_rxfull | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_targetidle | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_txempty | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
cp_txfull | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |