Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40227

1

T1

285

T2

53

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35566	1			T1	484		T2	89		T3	45
values[0x0]	15264	1			T1	153		T2	32		T3	17
values[0x1]	15939	1			T1	147		T2	28		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48097

1

T1

463

T2

94

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	242	1			T4	2		T5	11		T22	3
valid_sources[0x01]	210	1			T2	1		T4	1		T14	2
valid_sources[0x02]	269	1			T2	1		T4	1		T5	9
valid_sources[0x03]	241	1			T2	1		T8	1		T4	3
valid_sources[0x04]	208	1			T2	4		T8	3		T7	3
valid_sources[0x05]	242	1			T4	7		T14	1		T22	4
valid_sources[0x06]	222	1			T8	3		T4	5		T5	18
valid_sources[0x07]	228	1			T7	1		T4	1		T5	27
valid_sources[0x08]	159	1			T4	2		T5	15		T23	2
valid_sources[0x09]	216	1			T1	2		T4	1		T5	16
valid_sources[0x0a]	169	1			T2	1		T3	3		T8	3
valid_sources[0x0b]	279	1			T4	2		T5	2		T14	1
valid_sources[0x0c]	301	1			T1	8		T2	1		T4	2
valid_sources[0x0d]	335	1			T2	2		T4	2		T14	4
valid_sources[0x0e]	276	1			T4	4		T5	40		T15	3
valid_sources[0x0f]	366	1			T2	2		T8	5		T4	4
valid_sources[0x10]	266	1			T4	2		T22	2		T24	1
valid_sources[0x11]	189	1			T1	13		T2	1		T8	1
valid_sources[0x12]	212	1			T4	4		T5	23		T24	1
valid_sources[0x13]	477	1			T3	2		T4	2		T22	1
valid_sources[0x14]	246	1			T2	1		T3	5		T7	3
valid_sources[0x15]	203	1			T2	5		T4	3		T22	1
valid_sources[0x16]	210	1			T1	4		T2	1		T7	1
valid_sources[0x17]	277	1			T2	1		T4	3		T5	7
valid_sources[0x18]	193	1			T4	4		T5	21		T22	1
valid_sources[0x19]	236	1			T4	3		T5	15		T14	2
valid_sources[0x1a]	302	1			T7	2		T4	3		T5	3
valid_sources[0x1b]	218	1			T1	11		T2	1		T4	2
valid_sources[0x1c]	289	1			T2	3		T7	2		T4	2
valid_sources[0x1d]	366	1			T2	2		T3	2		T7	1
valid_sources[0x1e]	208	1			T2	2		T4	2		T5	9
valid_sources[0x1f]	174	1			T1	5		T2	1		T8	1
valid_sources[0x20]	184	1			T7	2		T5	2		T16	1
valid_sources[0x21]	242	1			T4	1		T22	3		T16	3
valid_sources[0x22]	240	1			T1	15		T4	4		T5	1
valid_sources[0x23]	176	1			T1	10		T8	1		T4	1
valid_sources[0x24]	346	1			T4	1		T14	4		T22	5
valid_sources[0x25]	249	1			T2	1		T7	1		T4	6
valid_sources[0x26]	291	1			T1	7		T2	1		T8	7
valid_sources[0x27]	234	1			T7	6		T4	4		T16	1
valid_sources[0x28]	218	1			T14	3		T22	1		T29	3
valid_sources[0x29]	244	1			T1	2		T16	2		T29	1
valid_sources[0x2a]	335	1			T2	1		T8	1		T4	1
valid_sources[0x2b]	308	1			T2	1		T4	1		T16	2
valid_sources[0x2c]	318	1			T8	2		T4	2		T22	1
valid_sources[0x2d]	280	1			T4	5		T5	12		T14	3
valid_sources[0x2e]	207	1			T2	1		T7	2		T4	6
valid_sources[0x2f]	198	1			T4	6		T5	9		T14	3
valid_sources[0x30]	218	1			T2	1		T4	2		T14	3
valid_sources[0x31]	210	1			T6	3		T4	1		T5	24
valid_sources[0x32]	246	1			T8	3		T4	5		T5	11
valid_sources[0x33]	263	1			T1	16		T22	3		T29	2
valid_sources[0x34]	274	1			T3	6		T4	3		T14	2
valid_sources[0x35]	247	1			T2	2		T4	2		T22	2
valid_sources[0x36]	262	1			T2	2		T3	12		T7	2
valid_sources[0x37]	221	1			T1	3		T8	1		T4	7
valid_sources[0x38]	175	1			T5	13		T14	1		T22	1
valid_sources[0x39]	202	1			T2	2		T7	3		T4	6
valid_sources[0x3a]	357	1			T1	17		T8	5		T4	6
valid_sources[0x3b]	200	1			T4	1		T5	17		T23	1
valid_sources[0x3c]	180	1			T8	2		T7	2		T4	5
valid_sources[0x3d]	279	1			T2	1		T4	2		T29	3
valid_sources[0x3e]	184	1			T2	1		T8	9		T4	6
valid_sources[0x3f]	234	1			T8	1		T7	6		T4	4
valid_sources[0x40]	299	1			T2	1		T4	3		T5	14
valid_sources[0x41]	214	1			T2	1		T4	2		T5	2
valid_sources[0x42]	256	1			T4	2		T5	11		T22	1
valid_sources[0x43]	208	1			T8	2		T4	2		T5	1
valid_sources[0x44]	145	1			T7	2		T4	1		T14	4
valid_sources[0x45]	343	1			T2	2		T4	1		T14	1
valid_sources[0x46]	296	1			T2	3		T4	1		T5	2
valid_sources[0x47]	193	1			T2	1		T4	6		T23	6
valid_sources[0x48]	310	1			T1	1		T8	2		T4	4
valid_sources[0x49]	253	1			T2	3		T4	4		T5	7
valid_sources[0x4a]	234	1			T4	6		T5	47		T14	3
valid_sources[0x4b]	318	1			T5	2		T14	1		T22	1
valid_sources[0x4c]	205	1			T3	5		T8	1		T4	5
valid_sources[0x4d]	229	1			T1	14		T2	1		T4	2
valid_sources[0x4e]	243	1			T2	1		T4	4		T5	18
valid_sources[0x4f]	250	1			T8	1		T4	2		T22	2
valid_sources[0x50]	270	1			T2	1		T4	4		T5	6
valid_sources[0x51]	215	1			T1	5		T4	6		T5	9
valid_sources[0x52]	199	1			T7	1		T4	2		T5	4
valid_sources[0x53]	375	1			T1	28		T4	4		T5	5
valid_sources[0x54]	289	1			T4	4		T14	1		T22	3
valid_sources[0x55]	269	1			T1	18		T4	6		T16	1
valid_sources[0x56]	359	1			T2	1		T3	1		T4	3
valid_sources[0x57]	216	1			T1	6		T4	1		T5	32
valid_sources[0x58]	388	1			T1	9		T2	1		T6	1
valid_sources[0x59]	188	1			T4	5		T5	2		T22	5
valid_sources[0x5a]	263	1			T2	1		T7	7		T4	3
valid_sources[0x5b]	279	1			T2	2		T4	4		T5	10
valid_sources[0x5c]	305	1			T4	1		T5	14		T14	1
valid_sources[0x5d]	226	1			T4	1		T29	1		T25	4
valid_sources[0x5e]	208	1			T2	1		T7	2		T4	4
valid_sources[0x5f]	254	1			T1	8		T2	1		T6	4
valid_sources[0x60]	269	1			T1	1		T4	3		T5	1
valid_sources[0x61]	186	1			T4	4		T14	1		T22	2
valid_sources[0x62]	235	1			T1	8		T2	1		T4	1
valid_sources[0x63]	202	1			T1	14		T2	2		T8	3
valid_sources[0x64]	201	1			T1	5		T2	1		T4	4
valid_sources[0x65]	249	1			T7	1		T4	2		T5	14
valid_sources[0x66]	272	1			T4	6		T24	1		T16	6
valid_sources[0x67]	213	1			T8	4		T4	3		T5	9
valid_sources[0x68]	211	1			T1	5		T2	1		T4	3
valid_sources[0x69]	269	1			T2	1		T4	1		T5	17
valid_sources[0x6a]	156	1			T2	2		T4	2		T5	3
valid_sources[0x6b]	316	1			T4	3		T14	2		T22	2
valid_sources[0x6c]	250	1			T4	1		T5	11		T22	2
valid_sources[0x6d]	280	1			T1	4		T8	1		T4	4
valid_sources[0x6e]	421	1			T4	6		T5	12		T24	1
valid_sources[0x6f]	392	1			T1	28		T6	2		T4	1
valid_sources[0x70]	252	1			T1	41		T2	1		T7	2
valid_sources[0x71]	204	1			T2	1		T4	2		T5	1
valid_sources[0x72]	289	1			T8	9		T4	6		T5	11
valid_sources[0x73]	246	1			T2	2		T3	11		T5	12
valid_sources[0x74]	481	1			T2	1		T7	3		T4	3
valid_sources[0x75]	238	1			T1	3		T4	2		T22	2
valid_sources[0x76]	213	1			T4	5		T5	28		T22	1
valid_sources[0x77]	217	1			T2	1		T4	2		T5	22
valid_sources[0x78]	202	1			T1	8		T2	3		T4	4
valid_sources[0x79]	324	1			T4	6		T22	4		T16	1
valid_sources[0x7a]	411	1			T8	2		T4	7		T22	1
valid_sources[0x7b]	237	1			T4	5		T5	21		T14	2
valid_sources[0x7c]	295	1			T1	1		T2	2		T4	5
valid_sources[0x7d]	235	1			T8	1		T4	2		T22	2
valid_sources[0x7e]	320	1			T1	1		T4	2		T14	1
valid_sources[0x7f]	175	1			T2	1		T4	2		T22	1
valid_sources[0x80]	455	1			T1	6		T7	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15624

1

T1

79

T2

11

T3

6

values[0x0]

all_enables

biggest_size

12784

1

T1

110

T2

22

T3

11

values[0x1]

all_enables

biggest_size

11819

1

T1

96

T2

20

T3

6