SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
0.00 | 0.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_host_cg | 0.00 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_target_cg | 0.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 8 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 8 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 8 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 8 | 0 | 0.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 8 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
b2b_read_different_addr | 0 | 1 | 1 | |
b2b_read_same_addr | 0 | 1 | 1 | |
write_after_read_different_addr | 0 | 1 | 1 | |
write_after_read_same_addr | 0 | 1 | 1 | |
read_after_write_different_addr | 0 | 1 | 1 | |
read_after_write_same_addr | 0 | 1 | 1 | |
b2b_write_different_addr | 0 | 1 | 1 | |
b2b_write_same_addr | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 8 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
b2b_read_different_addr | 0 | 1 | 1 | |
b2b_read_same_addr | 0 | 1 | 1 | |
write_after_read_different_addr | 0 | 1 | 1 | |
write_after_read_same_addr | 0 | 1 | 1 | |
read_after_write_different_addr | 0 | 1 | 1 | |
read_after_write_same_addr | 0 | 1 | 1 | |
b2b_write_different_addr | 0 | 1 | 1 | |
b2b_write_same_addr | 0 | 1 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |