Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_ram_1p
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic 0.00 0.00 0.00



Module Instance : tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS63600.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 0 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
==> MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 0 0.00
IF 63 3 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%