Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	641759	0	0	0
ctrl_rd_A	641759	2229	0	0
host_fifo_config_rd_A	641759	1206	0	0
host_nack_handler_timeout_rd_A	641759	1212	0	0
host_timeout_ctrl_rd_A	641759	1185	0	0
intr_enable_rd_A	641759	3345	0	0
ovrd_rd_A	641759	1412	0	0
target_fifo_config_rd_A	641759	1226	0	0
target_id_rd_A	641759	1575	0	0
target_timeout_ctrl_rd_A	641759	1318	0	0
timeout_ctrl_rd_A	641759	1425	0	0
timing0_rd_A	641759	1229	0	0
timing1_rd_A	641759	1273	0	0
timing2_rd_A	641759	1352	0	0
timing3_rd_A	641759	1246	0	0
timing4_rd_A	641759	1211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	2229	0	0
T4	8091	169	0	0
T5	13972	279	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	68	0	0
T19	0	25	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	124	0	0
T35	0	14	0	0
T46	0	33	0	0
T47	0	184	0	0
T48	0	205	0	0
T49	0	24	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1206	0	0
T4	8091	52	0	0
T5	13972	24	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	9	0	0
T19	0	14	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	144	0	0
T35	0	7	0	0
T46	0	23	0	0
T47	0	255	0	0
T48	0	57	0	0
T49	0	26	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1212	0	0
T4	8091	50	0	0
T5	13972	80	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	12	0	0
T19	0	18	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	102	0	0
T34	0	3	0	0
T35	0	3	0	0
T46	0	4	0	0
T47	0	221	0	0
T48	0	51	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1185	0	0
T4	8091	54	0	0
T5	13972	63	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	16	0	0
T15	1884	0	0	0
T16	4032	14	0	0
T19	0	8	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	109	0	0
T35	0	3	0	0
T46	0	13	0	0
T47	0	232	0	0
T48	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	3345	0	0
T4	8091	124	0	0
T5	13972	265	0	0
T10	1304	10	0	0
T12	887	0	0	0
T14	5003	15	0	0
T15	1884	0	0	0
T16	4032	21	0	0
T19	0	16	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	117	0	0
T35	0	6	0	0
T50	0	37	0	0
T51	0	18	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1412	0	0
T4	8091	56	0	0
T5	13972	106	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	3	0	0
T15	1884	0	0	0
T16	4032	26	0	0
T19	0	38	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	131	0	0
T34	0	8	0	0
T35	0	1	0	0
T46	0	16	0	0
T47	0	234	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1226	0	0
T4	8091	52	0	0
T5	13972	46	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	1	0	0
T15	1884	0	0	0
T16	4032	25	0	0
T19	0	24	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	103	0	0
T34	0	7	0	0
T46	0	27	0	0
T47	0	211	0	0
T48	0	46	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1575	0	0
T4	8091	89	0	0
T5	13972	101	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	41	0	0
T19	0	18	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	107	0	0
T35	0	19	0	0
T46	0	7	0	0
T47	0	216	0	0
T48	0	131	0	0
T49	0	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1318	0	0
T4	8091	56	0	0
T5	13972	72	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	6	0	0
T15	1884	0	0	0
T16	4032	47	0	0
T19	0	10	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	129	0	0
T34	0	6	0	0
T35	0	4	0	0
T46	0	27	0	0
T47	0	243	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1425	0	0
T4	8091	91	0	0
T5	13972	81	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	23	0	0
T15	1884	0	0	0
T16	4032	21	0	0
T19	0	12	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	130	0	0
T34	0	5	0	0
T35	0	1	0	0
T46	0	2	0	0
T47	0	242	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1229	0	0
T4	8091	75	0	0
T5	13972	58	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	5	0	0
T15	1884	0	0	0
T16	4032	3	0	0
T19	0	24	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	94	0	0
T34	0	2	0	0
T35	0	5	0	0
T47	0	226	0	0
T48	0	89	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1273	0	0
T4	8091	67	0	0
T5	13972	89	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	8	0	0
T15	1884	0	0	0
T16	4032	25	0	0
T19	0	23	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	104	0	0
T35	0	10	0	0
T46	0	2	0	0
T47	0	204	0	0
T48	0	81	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1352	0	0
T4	8091	82	0	0
T5	13972	49	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	11	0	0
T19	0	23	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	118	0	0
T35	0	1	0	0
T46	0	9	0	0
T47	0	226	0	0
T48	0	45	0	0
T49	0	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1246	0	0
T4	8091	78	0	0
T5	13972	75	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	11	0	0
T15	1884	0	0	0
T16	4032	32	0	0
T19	0	17	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	105	0	0
T35	0	17	0	0
T47	0	193	0	0
T48	0	76	0	0
T49	0	17	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641759	1211	0	0
T4	8091	80	0	0
T5	13972	49	0	0
T10	1304	0	0	0
T12	887	0	0	0
T14	5003	0	0	0
T15	1884	0	0	0
T16	4032	35	0	0
T19	0	17	0	0
T22	1659	0	0	0
T23	1266	0	0	0
T24	1024	0	0	0
T32	0	111	0	0
T35	0	2	0	0
T46	0	11	0	0
T47	0	220	0	0
T48	0	54	0	0
T49	0	12	0	0