Line Coverage for Module :
i2c
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
Cond Coverage for Module :
i2c
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 69
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T199,T200 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T10,T199,T200 |
Toggle Coverage for Module :
i2c
| Total | Covered | Percent |
Totals |
51 |
45 |
88.24 |
Total Bits |
394 |
370 |
93.91 |
Total Bits 0->1 |
197 |
185 |
93.91 |
Total Bits 1->0 |
197 |
185 |
93.91 |
| | | |
Ports |
51 |
45 |
88.24 |
Port Bits |
394 |
370 |
93.91 |
Port Bits 0->1 |
197 |
185 |
93.91 |
Port Bits 1->0 |
197 |
185 |
93.91 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T9,T33,T25 |
Yes |
T1,T2,T3 |
INPUT |
ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
tl_i.d_ready |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T3,T7 |
Yes |
T1,T3,T7 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T201,T153,T202 |
Yes |
T201,T153,T202 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T10,T199,T200 |
Yes |
T10,T199,T200 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T10,T199,T200 |
Yes |
T10,T199,T200 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T157,T15,T203 |
Yes |
T157,T15,T203 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T64,T33,T25 |
Yes |
T64,T33,T25 |
OUTPUT |
intr_controller_halt_o |
Yes |
Yes |
T9,T34,T31 |
Yes |
T9,T34,T31 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T9,T31,T32 |
Yes |
T9,T31,T32 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T9,T31,T32 |
Yes |
T9,T31,T32 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T9,T31,T32 |
Yes |
T9,T31,T32 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T2,T3,T6 |
Yes |
T2,T3,T6 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T3,T7,T9 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_acq_stretch_o |
Yes |
Yes |
T7,T11,T12 |
Yes |
T7,T11,T12 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T76,T155,T13 |
Yes |
T76,T155,T13 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T8,T68,T69 |
Yes |
T8,T68,T69 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
i2c
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
CioSclEnKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
CioSclKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
CioSdaEnKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
CioSdaKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
80 |
0 |
0 |
T162 |
382347 |
0 |
0 |
0 |
T204 |
6346 |
20 |
0 |
0 |
T205 |
0 |
20 |
0 |
0 |
T206 |
0 |
10 |
0 |
0 |
T207 |
0 |
20 |
0 |
0 |
T208 |
0 |
10 |
0 |
0 |
T209 |
1659 |
0 |
0 |
0 |
T210 |
178753 |
0 |
0 |
0 |
T211 |
21321 |
0 |
0 |
0 |
T212 |
140799 |
0 |
0 |
0 |
T213 |
1094 |
0 |
0 |
0 |
T214 |
1307 |
0 |
0 |
0 |
T215 |
26965 |
0 |
0 |
0 |
T216 |
16569 |
0 |
0 |
0 |
IntrAcqStretchKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrAcqWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrCommandCompleteKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrControllerHaltKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrFmtWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrHostTimeoutKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrRxOflwKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrRxWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrSclInterfKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrSdaInterfKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrSdaUnstableKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrStretchTimeoutKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrTxStretchKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrTxWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
IntrUnexpStopKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394016774 |
393850166 |
0 |
0 |
T1 |
100160 |
100067 |
0 |
0 |
T2 |
112302 |
112225 |
0 |
0 |
T3 |
27693 |
27626 |
0 |
0 |
T4 |
173527 |
173438 |
0 |
0 |
T5 |
155169 |
155069 |
0 |
0 |
T6 |
20922 |
20858 |
0 |
0 |
T7 |
55370 |
55297 |
0 |
0 |
T8 |
135960 |
135874 |
0 |
0 |
T9 |
22801 |
21874 |
0 |
0 |
T10 |
1233 |
1177 |
0 |
0 |