Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	394692675	0	0	0
ctrl_rd_A	394692675	1490	0	0
host_fifo_config_rd_A	394692675	4074	0	0
host_nack_handler_timeout_rd_A	394692675	1272	0	0
host_timeout_ctrl_rd_A	394692675	1201	0	0
intr_enable_rd_A	394692675	3272	0	0
ovrd_rd_A	394692675	2021	0	0
target_fifo_config_rd_A	394692675	1147	0	0
target_id_rd_A	394692675	1292	0	0
target_timeout_ctrl_rd_A	394692675	1089	0	0
timeout_ctrl_rd_A	394692675	1289	0	0
timing0_rd_A	394692675	1164	0	0
timing1_rd_A	394692675	1163	0	0
timing2_rd_A	394692675	1158	0	0
timing3_rd_A	394692675	1127	0	0
timing4_rd_A	394692675	1186	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1490	0	0
T95	5851	3	0	0
T96	5887	14	0	0
T97	63673	432	0	0
T98	1922	9	0	0
T99	1808	2	0	0
T100	3306	11	0	0
T101	9055	95	0	0
T102	13505	174	0	0
T103	3118	8	0	0
T104	2812	8	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	4074	0	0
T45	0	197	0	0
T105	509873	234	0	0
T106	0	177	0	0
T107	0	222	0	0
T108	0	391	0	0
T109	0	175	0	0
T110	0	171	0	0
T111	0	180	0	0
T112	0	122	0	0
T113	0	79	0	0
T114	19867	0	0	0
T115	717486	0	0	0
T116	12934	0	0	0
T117	67139	0	0	0
T118	77184	0	0	0
T119	66742	0	0	0
T120	134192	0	0	0
T121	65465	0	0	0
T122	41053	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1272	0	0
T95	5851	57	0	0
T96	5887	5	0	0
T97	63673	449	0	0
T98	1922	12	0	0
T99	1808	16	0	0
T101	9055	64	0	0
T102	13505	66	0	0
T103	3118	37	0	0
T123	3154	15	0	0
T124	2081	8	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1201	0	0
T95	5851	104	0	0
T96	5887	9	0	0
T97	63673	491	0	0
T98	1922	2	0	0
T99	1808	7	0	0
T100	3306	13	0	0
T101	9055	47	0	0
T102	13505	66	0	0
T103	3118	16	0	0
T124	2081	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	3272	0	0
T45	0	3	0	0
T53	999781	38	0	0
T95	0	57	0	0
T96	0	19	0	0
T97	0	436	0	0
T108	0	15	0	0
T112	0	13	0	0
T123	0	17	0	0
T125	0	8	0	0
T126	0	45	0	0
T127	11181	0	0	0
T128	2377	0	0	0
T129	73404	0	0	0
T130	188404	0	0	0
T131	157388	0	0	0
T132	949055	0	0	0
T133	8536	0	0	0
T134	43303	0	0	0
T135	29438	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	2021	0	0
T21	254571	0	0	0
T43	8782	0	0	0
T136	2151	37	0	0
T137	0	14	0	0
T138	0	39	0	0
T139	0	71	0	0
T140	0	25	0	0
T141	0	57	0	0
T142	0	34	0	0
T143	0	33	0	0
T144	0	43	0	0
T145	0	51	0	0
T146	2152	0	0	0
T147	202849	0	0	0
T148	131402	0	0	0
T149	3786	0	0	0
T150	118352	0	0	0
T151	47996	0	0	0
T152	845	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1147	0	0
T95	5851	22	0	0
T96	5887	10	0	0
T97	63673	470	0	0
T98	1922	8	0	0
T99	1808	12	0	0
T100	3306	17	0	0
T101	9055	41	0	0
T102	13505	55	0	0
T123	3154	36	0	0
T124	2081	9	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1292	0	0
T95	5851	20	0	0
T96	5887	5	0	0
T97	63673	440	0	0
T99	1808	10	0	0
T100	3306	4	0	0
T101	9055	85	0	0
T102	13505	112	0	0
T103	3118	3	0	0
T104	2812	14	0	0
T124	2081	35	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1089	0	0
T95	5851	62	0	0
T96	5887	1	0	0
T97	63673	421	0	0
T98	1922	17	0	0
T99	1808	9	0	0
T100	3306	17	0	0
T101	9055	57	0	0
T102	13505	41	0	0
T123	3154	36	0	0
T124	2081	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1289	0	0
T95	5851	29	0	0
T96	5887	20	0	0
T97	63673	406	0	0
T98	1922	12	0	0
T99	1808	8	0	0
T100	3306	8	0	0
T101	9055	92	0	0
T102	13505	63	0	0
T123	3154	22	0	0
T124	2081	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1164	0	0
T95	5851	64	0	0
T96	5887	13	0	0
T97	63673	449	0	0
T98	1922	2	0	0
T99	1808	8	0	0
T100	3306	7	0	0
T101	9055	63	0	0
T102	13505	61	0	0
T123	3154	8	0	0
T124	2081	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1163	0	0
T95	5851	26	0	0
T96	5887	23	0	0
T97	63673	452	0	0
T98	1922	6	0	0
T99	1808	15	0	0
T100	3306	10	0	0
T101	9055	39	0	0
T102	13505	36	0	0
T123	3154	31	0	0
T124	2081	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1158	0	0
T95	5851	53	0	0
T96	5887	31	0	0
T97	63673	421	0	0
T99	1808	22	0	0
T100	3306	20	0	0
T101	9055	78	0	0
T102	13505	53	0	0
T104	2812	7	0	0
T123	3154	13	0	0
T124	2081	2	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1127	0	0
T95	5851	36	0	0
T96	5887	34	0	0
T97	63673	403	0	0
T98	1922	10	0	0
T99	1808	24	0	0
T100	3306	26	0	0
T101	9055	76	0	0
T102	13505	85	0	0
T123	3154	18	0	0
T124	2081	15	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394692675	1186	0	0
T95	5851	44	0	0
T96	5887	2	0	0
T97	63673	470	0	0
T98	1922	9	0	0
T99	1808	8	0	0
T100	3306	19	0	0
T101	9055	64	0	0
T102	13505	47	0	0
T123	3154	50	0	0
T124	2081	5	0	0