Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.08	100.00	84.31			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.08	100.00	84.31			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	459836787	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	459836787	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	459836787	0	0
T1	20292	7391	0	0
T2	2316	0	0	0
T3	734048	176026	0	0
T4	1063624	68005	0	0
T5	1038144	1375	0	0
T6	318088	38550	0	0
T7	917080	110179	0	0
T8	115432	12404	0	0
T9	256648	8294	0	0
T10	7480	0	0	0
T11	0	202293	0	0
T16	196062	14320	0	0
T24	0	729850	0	0
T25	0	256	0	0
T26	0	9930	0	0
T30	34206	4972	0	0
T31	997976	242910	0	0
T35	0	261252	0	0
T38	0	1879	0	0
T42	0	38728	0	0
T43	0	512	0	0
T91	0	608	0	0
T159	0	322057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	81168	80384	0	0
T2	9264	8688	0	0
T3	1468096	1467320	0	0
T4	1063624	1063136	0	0
T5	1038144	1037432	0	0
T6	318088	317600	0	0
T7	917080	916552	0	0
T8	115432	114680	0	0
T9	256648	256248	0	0
T10	7480	6760	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	81168	80384	0	0
T2	9264	8688	0	0
T3	1468096	1467320	0	0
T4	1063624	1063136	0	0
T5	1038144	1037432	0	0
T6	318088	317600	0	0
T7	917080	916552	0	0
T8	115432	114680	0	0
T9	256648	256248	0	0
T10	7480	6760	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	81168	80384	0	0
T2	9264	8688	0	0
T3	1468096	1467320	0	0
T4	1063624	1063136	0	0
T5	1038144	1037432	0	0
T6	318088	317600	0	0
T7	917080	916552	0	0
T8	115432	114680	0	0
T9	256648	256248	0	0
T10	7480	6760	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	459836787	0	0
T1	20292	7391	0	0
T2	2316	0	0	0
T3	734048	176026	0	0
T4	1063624	68005	0	0
T5	1038144	1375	0	0
T6	318088	38550	0	0
T7	917080	110179	0	0
T8	115432	12404	0	0
T9	256648	8294	0	0
T10	7480	0	0	0
T11	0	202293	0	0
T16	196062	14320	0	0
T24	0	729850	0	0
T25	0	256	0	0
T26	0	9930	0	0
T30	34206	4972	0	0
T31	997976	242910	0	0
T35	0	261252	0	0
T38	0	1879	0	0
T42	0	38728	0	0
T43	0	512	0	0
T91	0	608	0	0
T159	0	322057	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T85,T56,T72
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T85,T56,T72
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	193433	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	193433	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	193433	0	0
T1	10146	12	0	0
T2	1158	0	0	0
T3	183512	149	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	179	0	0
T7	114635	82	0	0
T8	14429	2	0	0
T9	32081	0	0	0
T10	935	0	0	0
T30	0	2	0	0
T31	0	40	0	0
T35	0	9	0	0
T38	0	27	0	0
T42	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	193433	0	0
T1	10146	12	0	0
T2	1158	0	0	0
T3	183512	149	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	179	0	0
T7	114635	82	0	0
T8	14429	2	0	0
T9	32081	0	0	0
T10	935	0	0	0
T30	0	2	0	0
T31	0	40	0	0
T35	0	9	0	0
T38	0	27	0	0
T42	0	23	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T37,T52,T108
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T37,T52,T108
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	366899	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	366899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	366899	0	0
T3	183512	884	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	0	0	0
T7	114635	512	0	0
T8	14429	64	0	0
T9	32081	0	0	0
T10	935	0	0	0
T16	32677	0	0	0
T30	5701	0	0	0
T31	0	1280	0	0
T35	0	287	0	0
T38	0	2	0	0
T42	0	167	0	0
T43	0	512	0	0
T46	0	16	0	0
T85	0	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	366899	0	0
T3	183512	884	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	0	0	0
T7	114635	512	0	0
T8	14429	64	0	0
T9	32081	0	0	0
T10	935	0	0	0
T16	32677	0	0	0
T30	5701	0	0	0
T31	0	1280	0	0
T35	0	287	0	0
T38	0	2	0	0
T42	0	167	0	0
T43	0	512	0	0
T46	0	16	0	0
T85	0	119	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T87,T160,T161
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T87,T160,T161
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	83246	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	83246	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	83246	0	0
T4	132953	290	0	0
T5	129768	574	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	76	0	0
T10	935	0	0	0
T16	32677	41	0	0
T24	0	149	0	0
T25	0	286	0	0
T26	0	56	0	0
T27	0	86	0	0
T28	0	64	0	0
T29	0	30	0	0
T30	5701	0	0	0
T31	249494	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	83246	0	0
T4	132953	290	0	0
T5	129768	574	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	76	0	0
T10	935	0	0	0
T16	32677	41	0	0
T24	0	149	0	0
T25	0	286	0	0
T26	0	56	0	0
T27	0	86	0	0
T28	0	64	0	0
T29	0	30	0	0
T30	5701	0	0	0
T31	249494	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T162,T163
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T162,T163
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	139787	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	139787	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	139787	0	0
T4	132953	384	0	0
T5	129768	69	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	90	0	0
T10	935	0	0	0
T11	0	817	0	0
T16	32677	109	0	0
T24	0	195	0	0
T25	0	32	0	0
T26	0	6	0	0
T30	5701	0	0	0
T31	249494	0	0	0
T91	0	5	0	0
T159	0	151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	139787	0	0
T4	132953	384	0	0
T5	129768	69	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	90	0	0
T10	935	0	0	0
T11	0	817	0	0
T16	32677	109	0	0
T24	0	195	0	0
T25	0	32	0	0
T26	0	6	0	0
T30	5701	0	0	0
T31	249494	0	0	0
T91	0	5	0	0
T159	0	151	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T31

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T31,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	37390966	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	37390966	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	37390966	0	0
T3	183512	19419	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	0	0	0
T7	114635	11446	0	0
T8	14429	11911	0	0
T9	32081	0	0	0
T10	935	0	0	0
T16	32677	0	0	0
T30	5701	0	0	0
T31	0	238892	0	0
T35	0	6388	0	0
T38	0	36	0	0
T42	0	1047	0	0
T43	0	34826	0	0
T46	0	369	0	0
T85	0	4336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	37390966	0	0
T3	183512	19419	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	0	0	0
T7	114635	11446	0	0
T8	14429	11911	0	0
T9	32081	0	0	0
T10	935	0	0	0
T16	32677	0	0	0
T30	5701	0	0	0
T31	0	238892	0	0
T35	0	6388	0	0
T38	0	36	0	0
T42	0	1047	0	0
T43	0	34826	0	0
T46	0	369	0	0
T85	0	4336	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	63245889	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	63245889	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	63245889	0	0
T4	132953	60874	0	0
T5	129768	119903	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	13853	0	0
T10	935	0	0	0
T16	32677	8334	0	0
T24	0	715348	0	0
T25	0	48199	0	0
T26	0	10920	0	0
T27	0	16694	0	0
T28	0	10655	0	0
T29	0	6247	0	0
T30	5701	0	0	0
T31	249494	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	63245889	0	0
T4	132953	60874	0	0
T5	129768	119903	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	13853	0	0
T10	935	0	0	0
T16	32677	8334	0	0
T24	0	715348	0	0
T25	0	48199	0	0
T26	0	10920	0	0
T27	0	16694	0	0
T28	0	10655	0	0
T29	0	6247	0	0
T30	5701	0	0	0
T31	249494	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	190998789	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	190998789	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	190998789	0	0
T4	132953	67621	0	0
T5	129768	1306	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	8204	0	0
T10	935	0	0	0
T11	0	201476	0	0
T16	32677	14211	0	0
T24	0	729655	0	0
T25	0	224	0	0
T26	0	9924	0	0
T30	5701	0	0	0
T31	249494	0	0	0
T91	0	603	0	0
T159	0	321906	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	190998789	0	0
T4	132953	67621	0	0
T5	129768	1306	0	0
T6	39761	0	0	0
T7	114635	0	0	0
T8	14429	0	0	0
T9	32081	8204	0	0
T10	935	0	0	0
T11	0	201476	0	0
T16	32677	14211	0	0
T24	0	729655	0	0
T25	0	224	0	0
T26	0	9924	0	0
T30	5701	0	0	0
T31	249494	0	0	0
T91	0	603	0	0
T159	0	321906	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T33,T34
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T6,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	384424115	167417778	0	0
DepthKnown_A	384424115	384245870	0	0
RvalidKnown_A	384424115	384245870	0	0
WreadyKnown_A	384424115	384245870	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	384424115	167417778	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	167417778	0	0
T1	10146	7379	0	0
T2	1158	0	0	0
T3	183512	174993	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	38371	0	0
T7	114635	109585	0	0
T8	14429	12338	0	0
T9	32081	0	0	0
T10	935	0	0	0
T30	0	4970	0	0
T31	0	241590	0	0
T35	0	260956	0	0
T38	0	1850	0	0
T42	0	38538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	384245870	0	0
T1	10146	10048	0	0
T2	1158	1086	0	0
T3	183512	183415	0	0
T4	132953	132892	0	0
T5	129768	129679	0	0
T6	39761	39700	0	0
T7	114635	114569	0	0
T8	14429	14335	0	0
T9	32081	32031	0	0
T10	935	845	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	384424115	167417778	0	0
T1	10146	7379	0	0
T2	1158	0	0	0
T3	183512	174993	0	0
T4	132953	0	0	0
T5	129768	0	0	0
T6	39761	38371	0	0
T7	114635	109585	0	0
T8	14429	12338	0	0
T9	32081	0	0	0
T10	935	0	0	0
T30	0	4970	0	0
T31	0	241590	0	0
T35	0	260956	0	0
T38	0	1850	0	0
T42	0	38538	0	0