Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	326	1			T6	1		T18	1		T9	8
all_values[1]	326	1			T6	1		T18	1		T9	8
all_values[2]	326	1			T6	1		T18	1		T9	8
all_values[3]	326	1			T6	1		T18	1		T9	8
all_values[4]	326	1			T6	1		T18	1		T9	8
all_values[5]	326	1			T6	1		T18	1		T9	8
all_values[6]	326	1			T6	1		T18	1		T9	8
all_values[7]	326	1			T6	1		T18	1		T9	8
all_values[8]	326	1			T6	1		T18	1		T9	8
all_values[9]	326	1			T6	1		T18	1		T9	8
all_values[10]	326	1			T6	1		T18	1		T9	8
all_values[11]	326	1			T6	1		T18	1		T9	8
all_values[12]	326	1			T6	1		T18	1		T9	8
all_values[13]	326	1			T6	1		T18	1		T9	8
all_values[14]	326	1			T6	1		T18	1		T9	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3182

1

T6

15

T18

15

T9

78

auto[1]

1708

1

T9

42

T10

30

T11

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T6

15

T18

15

T9

16

auto[1]

3894

1

T9

104

T10

66

T11

105

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	67	1			T6	1		T18	1		T9	2
all_values[0]	auto[0]	auto[1]	158	1			T9	4		T10	3		T11	4
all_values[0]	auto[1]	auto[1]	101	1			T9	2		T10	2		T11	1
all_values[1]	auto[0]	auto[0]	69	1			T6	1		T18	1		T9	2
all_values[1]	auto[0]	auto[1]	149	1			T9	3		T10	2		T11	2
all_values[1]	auto[1]	auto[1]	108	1			T9	3		T10	3		T11	1
all_values[2]	auto[0]	auto[0]	61	1			T6	1		T18	1		T9	2
all_values[2]	auto[0]	auto[1]	158	1			T9	4		T10	2		T11	4
all_values[2]	auto[1]	auto[1]	107	1			T9	2		T10	1		T11	4
all_values[3]	auto[0]	auto[0]	66	1			T6	1		T18	1		T9	4
all_values[3]	auto[0]	auto[1]	136	1			T9	1		T10	3		T11	4
all_values[3]	auto[1]	auto[1]	124	1			T9	3		T10	1		T11	4
all_values[4]	auto[0]	auto[0]	84	1			T6	1		T18	1		T9	2
all_values[4]	auto[0]	auto[1]	149	1			T9	4		T10	3		T11	5
all_values[4]	auto[1]	auto[1]	93	1			T9	2		T10	2		T11	3
all_values[5]	auto[0]	auto[0]	55	1			T6	1		T18	1		T19	1
all_values[5]	auto[0]	auto[1]	142	1			T9	4		T10	2		T11	3
all_values[5]	auto[1]	auto[1]	129	1			T9	4		T10	3		T11	4
all_values[6]	auto[0]	auto[0]	74	1			T6	1		T18	1		T19	1
all_values[6]	auto[0]	auto[1]	123	1			T9	4		T11	1		T15	3
all_values[6]	auto[1]	auto[1]	129	1			T9	4		T11	6		T15	2
all_values[7]	auto[0]	auto[0]	55	1			T6	1		T18	1		T9	1
all_values[7]	auto[0]	auto[1]	139	1			T9	5		T10	1		T11	5
all_values[7]	auto[1]	auto[1]	132	1			T9	2		T10	3		T11	3
all_values[8]	auto[0]	auto[0]	53	1			T6	1		T18	1		T9	2
all_values[8]	auto[0]	auto[1]	158	1			T9	5		T10	3		T11	6
all_values[8]	auto[1]	auto[1]	115	1			T9	1		T10	2		T11	2
all_values[9]	auto[0]	auto[0]	63	1			T6	1		T18	1		T9	1
all_values[9]	auto[0]	auto[1]	144	1			T9	6		T10	1		T11	5
all_values[9]	auto[1]	auto[1]	119	1			T9	1		T10	4		T11	2
all_values[10]	auto[0]	auto[0]	77	1			T6	1		T18	1		T19	1
all_values[10]	auto[0]	auto[1]	149	1			T9	4		T10	3		T11	5
all_values[10]	auto[1]	auto[1]	100	1			T9	4		T10	2		T11	2
all_values[11]	auto[0]	auto[0]	75	1			T6	1		T18	1		T19	1
all_values[11]	auto[0]	auto[1]	149	1			T9	4		T10	3		T11	4
all_values[11]	auto[1]	auto[1]	102	1			T9	4		T10	2		T11	4
all_values[12]	auto[0]	auto[0]	54	1			T6	1		T18	1		T19	1
all_values[12]	auto[0]	auto[1]	168	1			T9	7		T10	3		T11	4
all_values[12]	auto[1]	auto[1]	104	1			T9	1		T10	2		T11	3
all_values[13]	auto[0]	auto[0]	78	1			T6	1		T18	1		T19	1
all_values[13]	auto[0]	auto[1]	127	1			T9	4		T10	4		T11	1
all_values[13]	auto[1]	auto[1]	121	1			T9	4		T10	1		T11	5
all_values[14]	auto[0]	auto[0]	65	1			T6	1		T18	1		T19	1
all_values[14]	auto[0]	auto[1]	137	1			T9	3		T10	3		T11	3
all_values[14]	auto[1]	auto[1]	124	1			T9	5		T10	2		T11	5