Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
52.68	40.66	40.72	90.72	0.00	42.98	99.68	54.00

Total tests in report: 160

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
45.58	45.58	39.00	39.00	36.85	36.85	93.30	93.30	0.00	0.00	41.70	41.70	90.76	90.76	17.47	17.47	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.89376651
50.59	5.01	40.20	1.19	39.03	2.18	96.28	2.98	0.00	0.00	42.91	1.21	91.08	0.32	44.63	27.16	/workspace/coverage/cover_reg_top/27.i2c_intr_test.825955524
52.13	1.55	40.20	0.00	39.97	0.94	96.77	0.50	0.00	0.00	42.98	0.07	96.82	5.73	48.21	3.58	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2498428869
52.60	0.46	40.66	0.46	40.08	0.11	96.77	0.00	0.00	0.00	42.98	0.00	99.36	2.55	48.32	0.11	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2690820685
53.01	0.41	40.66	0.00	40.08	0.00	97.02	0.25	0.00	0.00	42.98	0.00	99.36	0.00	50.95	2.63	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1208923239
53.13	0.12	40.66	0.00	40.08	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.32	51.47	0.53	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4256732467
53.23	0.11	40.66	0.00	40.08	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.21	0.74	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2143746638
53.31	0.08	40.66	0.00	40.31	0.23	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.53	0.32	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4065306150
53.39	0.08	40.66	0.00	40.31	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.05	0.53	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1522438606
53.43	0.05	40.66	0.00	40.31	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.37	0.32	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1598862284
53.46	0.03	40.66	0.00	40.31	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.58	0.21	/workspace/coverage/cover_reg_top/28.i2c_intr_test.535939874
53.49	0.03	40.66	0.00	40.50	0.19	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.58	0.00	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2729090944
53.50	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.68	0.11	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1040547848
53.52	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.11	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1485195088
53.53	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.89	0.11	/workspace/coverage/cover_reg_top/20.i2c_intr_test.2682925980
53.55	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.11	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2878472811
53.56	0.01	40.66	0.00	40.57	0.08	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.863086704
53.56	0.01	40.66	0.00	40.61	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1720079837
53.57	0.01	40.66	0.00	40.65	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3468341036
53.57	0.01	40.66	0.00	40.68	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2989281346
53.58	0.01	40.66	0.00	40.72	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4140500856

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.212089695
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1055360388
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3426919527
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1401599523
/workspace/coverage/cover_reg_top/0.i2c_intr_test.864030547
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3520519819
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.770380582
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.767430290
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3851491858
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4003552204
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1589021098
/workspace/coverage/cover_reg_top/1.i2c_intr_test.2905000109
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3619673964
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2046148420
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1823762282
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1814052409
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2452480447
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1176827544
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1469170119
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4020388257
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1392118853
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3517054102
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1753884885
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1053022010
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3050796071
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.4120937924
/workspace/coverage/cover_reg_top/12.i2c_intr_test.3302859773
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.688853104
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1206426021
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.473579358
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3367084188
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3689365022
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2898009726
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1578565600
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1685841320
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3121400829
/workspace/coverage/cover_reg_top/14.i2c_intr_test.874534238
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1956840914
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3837727418
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1796605465
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.206029090
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.447693548
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1178804397
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1242542607
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.995030235
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2437122843
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1462808533
/workspace/coverage/cover_reg_top/16.i2c_intr_test.2549300699
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3464737892
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.966943604
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2335971619
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2988103156
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1772872459
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2924023431
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3784311874
/workspace/coverage/cover_reg_top/18.i2c_intr_test.1783534998
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2947051353
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.628036777
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1162919190
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2797995097
/workspace/coverage/cover_reg_top/19.i2c_intr_test.1661064046
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3921097415
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3008551546
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1681881009
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3448391427
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3034444750
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4111234949
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2545345744
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3807391691
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1719104327
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1213854980
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4283827262
/workspace/coverage/cover_reg_top/21.i2c_intr_test.1542151025
/workspace/coverage/cover_reg_top/22.i2c_intr_test.3279830095
/workspace/coverage/cover_reg_top/23.i2c_intr_test.2480720185
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1640423235
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3701121646
/workspace/coverage/cover_reg_top/26.i2c_intr_test.3540822544
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3972185176
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2988605425
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1771912083
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1313408334
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3807593942
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2747438744
/workspace/coverage/cover_reg_top/3.i2c_intr_test.543428941
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2366051050
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2201077207
/workspace/coverage/cover_reg_top/30.i2c_intr_test.3113968310
/workspace/coverage/cover_reg_top/31.i2c_intr_test.3419815321
/workspace/coverage/cover_reg_top/32.i2c_intr_test.412937859
/workspace/coverage/cover_reg_top/33.i2c_intr_test.62390587
/workspace/coverage/cover_reg_top/34.i2c_intr_test.259435901
/workspace/coverage/cover_reg_top/35.i2c_intr_test.3938629125
/workspace/coverage/cover_reg_top/36.i2c_intr_test.224522195
/workspace/coverage/cover_reg_top/37.i2c_intr_test.832708443
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3970350774
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3366298933
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1080378475
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2177098543
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3218453804
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2042932372
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1413821500
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.795193555
/workspace/coverage/cover_reg_top/40.i2c_intr_test.1369210548
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1678066274
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3704194756
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3629066899
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2905210851
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2045337015
/workspace/coverage/cover_reg_top/46.i2c_intr_test.559746037
/workspace/coverage/cover_reg_top/47.i2c_intr_test.393713558
/workspace/coverage/cover_reg_top/48.i2c_intr_test.3632758250
/workspace/coverage/cover_reg_top/49.i2c_intr_test.754437831
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.385531226
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3243818891
/workspace/coverage/cover_reg_top/5.i2c_intr_test.3153134186
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1024051541
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1382573355
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4236699394
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.3281362800
/workspace/coverage/cover_reg_top/6.i2c_intr_test.226269427
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.61904248
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2086777419
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1789183863
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3415013538
/workspace/coverage/cover_reg_top/7.i2c_intr_test.3845219491
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4067778357
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.840489999
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1871637236
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.66328800
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.923710123
/workspace/coverage/cover_reg_top/8.i2c_intr_test.2975736667
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.637583586
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.74761295
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2024573926
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.2957697669
/workspace/coverage/cover_reg_top/9.i2c_intr_test.118479873
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3245194061
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.148553858

Total test records in report: 160

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.767430290	Jul 01 10:44:22 AM PDT 24	Jul 01 10:44:24 AM PDT 24	132876421 ps
T2	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4065306150	Jul 01 10:43:57 AM PDT 24	Jul 01 10:44:04 AM PDT 24	649565984 ps
T3	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2335971619	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	22731493 ps
T7	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1055360388	Jul 01 10:44:16 AM PDT 24	Jul 01 10:44:19 AM PDT 24	76183420 ps
T6	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2498428869	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:28 AM PDT 24	209715526 ps
T16	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2042932372	Jul 01 10:44:21 AM PDT 24	Jul 01 10:44:23 AM PDT 24	23939215 ps
T17	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4256732467	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:14 AM PDT 24	21459589 ps
T4	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.385531226	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:14 AM PDT 24	34746974 ps
T14	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1598862284	Jul 01 10:44:18 AM PDT 24	Jul 01 10:44:20 AM PDT 24	29689793 ps
T5	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.89376651	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:19 AM PDT 24	708188971 ps
T24	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1080378475	Jul 01 10:44:36 AM PDT 24	Jul 01 10:44:41 AM PDT 24	76690455 ps
T18	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2898009726	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	42152893 ps
T8	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1206426021	Jul 01 10:44:35 AM PDT 24	Jul 01 10:44:37 AM PDT 24	47268147 ps
T9	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1208923239	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	18910630 ps
T19	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1176827544	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:15 AM PDT 24	463774410 ps
T10	/workspace/coverage/cover_reg_top/9.i2c_intr_test.118479873	Jul 01 10:44:09 AM PDT 24	Jul 01 10:44:11 AM PDT 24	43032098 ps
T11	/workspace/coverage/cover_reg_top/27.i2c_intr_test.825955524	Jul 01 10:44:45 AM PDT 24	Jul 01 10:44:46 AM PDT 24	29372578 ps
T15	/workspace/coverage/cover_reg_top/8.i2c_intr_test.2975736667	Jul 01 10:44:09 AM PDT 24	Jul 01 10:44:11 AM PDT 24	38318124 ps
T12	/workspace/coverage/cover_reg_top/30.i2c_intr_test.3113968310	Jul 01 10:44:27 AM PDT 24	Jul 01 10:44:28 AM PDT 24	17883129 ps
T20	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4236699394	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:13 AM PDT 24	22918527 ps
T13	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3807391691	Jul 01 10:43:57 AM PDT 24	Jul 01 10:44:01 AM PDT 24	14744990 ps
T72	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1522438606	Jul 01 10:44:21 AM PDT 24	Jul 01 10:44:23 AM PDT 24	61535433 ps
T27	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2690820685	Jul 01 10:44:09 AM PDT 24	Jul 01 10:44:11 AM PDT 24	31405680 ps
T28	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3366298933	Jul 01 10:44:05 AM PDT 24	Jul 01 10:44:08 AM PDT 24	205200107 ps
T29	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2747438744	Jul 01 10:44:21 AM PDT 24	Jul 01 10:44:23 AM PDT 24	29948767 ps
T73	/workspace/coverage/cover_reg_top/32.i2c_intr_test.412937859	Jul 01 10:44:40 AM PDT 24	Jul 01 10:44:41 AM PDT 24	31283723 ps
T75	/workspace/coverage/cover_reg_top/40.i2c_intr_test.1369210548	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	20735939 ps
T21	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.206029090	Jul 01 10:44:22 AM PDT 24	Jul 01 10:44:24 AM PDT 24	26104128 ps
T30	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3448391427	Jul 01 10:43:59 AM PDT 24	Jul 01 10:44:07 AM PDT 24	138515580 ps
T22	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3468341036	Jul 01 10:44:16 AM PDT 24	Jul 01 10:44:19 AM PDT 24	87967913 ps
T52	/workspace/coverage/cover_reg_top/35.i2c_intr_test.3938629125	Jul 01 10:44:41 AM PDT 24	Jul 01 10:44:43 AM PDT 24	119337997 ps
T76	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1178804397	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:24 AM PDT 24	21478836 ps
T83	/workspace/coverage/cover_reg_top/19.i2c_intr_test.1661064046	Jul 01 10:44:49 AM PDT 24	Jul 01 10:44:50 AM PDT 24	28729364 ps
T44	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.4120937924	Jul 01 10:44:19 AM PDT 24	Jul 01 10:44:20 AM PDT 24	24360832 ps
T23	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2086777419	Jul 01 10:44:19 AM PDT 24	Jul 01 10:44:21 AM PDT 24	81549626 ps
T45	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4067778357	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:14 AM PDT 24	158716919 ps
T25	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1753884885	Jul 01 10:44:50 AM PDT 24	Jul 01 10:44:53 AM PDT 24	563358595 ps
T74	/workspace/coverage/cover_reg_top/14.i2c_intr_test.874534238	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	28475728 ps
T31	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3464737892	Jul 01 10:44:33 AM PDT 24	Jul 01 10:44:34 AM PDT 24	66809252 ps
T32	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3121400829	Jul 01 10:44:27 AM PDT 24	Jul 01 10:44:29 AM PDT 24	23187483 ps
T53	/workspace/coverage/cover_reg_top/49.i2c_intr_test.754437831	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:28 AM PDT 24	16124836 ps
T46	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2452480447	Jul 01 10:44:16 AM PDT 24	Jul 01 10:44:18 AM PDT 24	68286884 ps
T81	/workspace/coverage/cover_reg_top/5.i2c_intr_test.3153134186	Jul 01 10:44:34 AM PDT 24	Jul 01 10:44:36 AM PDT 24	49434720 ps
T26	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2024573926	Jul 01 10:44:13 AM PDT 24	Jul 01 10:44:15 AM PDT 24	154265776 ps
T84	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.923710123	Jul 01 10:44:07 AM PDT 24	Jul 01 10:44:09 AM PDT 24	43133441 ps
T77	/workspace/coverage/cover_reg_top/20.i2c_intr_test.2682925980	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	43885265 ps
T33	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2878472811	Jul 01 10:44:07 AM PDT 24	Jul 01 10:44:09 AM PDT 24	79757491 ps
T60	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.770380582	Jul 01 10:44:02 AM PDT 24	Jul 01 10:44:04 AM PDT 24	51616994 ps
T85	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3970350774	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:28 AM PDT 24	28069009 ps
T54	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1678066274	Jul 01 10:44:42 AM PDT 24	Jul 01 10:44:43 AM PDT 24	19554226 ps
T62	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2177098543	Jul 01 10:44:15 AM PDT 24	Jul 01 10:44:16 AM PDT 24	59146368 ps
T71	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4283827262	Jul 01 10:43:58 AM PDT 24	Jul 01 10:44:03 AM PDT 24	51252710 ps
T61	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2366051050	Jul 01 10:44:05 AM PDT 24	Jul 01 10:44:08 AM PDT 24	36054245 ps
T58	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2989281346	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:26 AM PDT 24	306707447 ps
T47	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2729090944	Jul 01 10:44:41 AM PDT 24	Jul 01 10:44:43 AM PDT 24	443810543 ps
T48	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2988103156	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	375254365 ps
T86	/workspace/coverage/cover_reg_top/34.i2c_intr_test.259435901	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:27 AM PDT 24	36909657 ps
T51	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3921097415	Jul 01 10:44:44 AM PDT 24	Jul 01 10:44:46 AM PDT 24	99484631 ps
T87	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1823762282	Jul 01 10:44:40 AM PDT 24	Jul 01 10:44:42 AM PDT 24	323580055 ps
T88	/workspace/coverage/cover_reg_top/23.i2c_intr_test.2480720185	Jul 01 10:44:36 AM PDT 24	Jul 01 10:44:38 AM PDT 24	15611735 ps
T89	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.840489999	Jul 01 10:44:36 AM PDT 24	Jul 01 10:44:40 AM PDT 24	76823199 ps
T90	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1720079837	Jul 01 10:44:18 AM PDT 24	Jul 01 10:44:21 AM PDT 24	402038600 ps
T91	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3689365022	Jul 01 10:44:45 AM PDT 24	Jul 01 10:44:47 AM PDT 24	100149927 ps
T92	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1772872459	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:19 AM PDT 24	633038724 ps
T34	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.3281362800	Jul 01 10:44:39 AM PDT 24	Jul 01 10:44:40 AM PDT 24	75563995 ps
T49	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2201077207	Jul 01 10:44:07 AM PDT 24	Jul 01 10:44:11 AM PDT 24	623797503 ps
T82	/workspace/coverage/cover_reg_top/18.i2c_intr_test.1783534998	Jul 01 10:44:47 AM PDT 24	Jul 01 10:44:48 AM PDT 24	87415555 ps
T93	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3520519819	Jul 01 10:44:37 AM PDT 24	Jul 01 10:44:39 AM PDT 24	34150195 ps
T50	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1796605465	Jul 01 10:44:16 AM PDT 24	Jul 01 10:44:19 AM PDT 24	466064114 ps
T94	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3619673964	Jul 01 10:44:09 AM PDT 24	Jul 01 10:44:12 AM PDT 24	157794995 ps
T95	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3426919527	Jul 01 10:43:58 AM PDT 24	Jul 01 10:44:03 AM PDT 24	66699167 ps
T96	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1469170119	Jul 01 10:44:21 AM PDT 24	Jul 01 10:44:23 AM PDT 24	47287543 ps
T97	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1024051541	Jul 01 10:44:50 AM PDT 24	Jul 01 10:44:56 AM PDT 24	49715890 ps
T98	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3050796071	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:14 AM PDT 24	52339105 ps
T99	/workspace/coverage/cover_reg_top/42.i2c_intr_test.3704194756	Jul 01 10:44:48 AM PDT 24	Jul 01 10:44:49 AM PDT 24	20266848 ps
T100	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4111234949	Jul 01 10:44:11 AM PDT 24	Jul 01 10:44:12 AM PDT 24	207158181 ps
T101	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3517054102	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:18 AM PDT 24	23138821 ps
T102	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1789183863	Jul 01 10:44:33 AM PDT 24	Jul 01 10:44:35 AM PDT 24	28565019 ps
T103	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1392118853	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:18 AM PDT 24	52162511 ps
T63	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1578565600	Jul 01 10:44:32 AM PDT 24	Jul 01 10:44:34 AM PDT 24	95822582 ps
T104	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1213854980	Jul 01 10:43:59 AM PDT 24	Jul 01 10:44:05 AM PDT 24	430099485 ps
T59	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.795193555	Jul 01 10:44:28 AM PDT 24	Jul 01 10:44:30 AM PDT 24	285310250 ps
T105	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3972185176	Jul 01 10:44:35 AM PDT 24	Jul 01 10:44:37 AM PDT 24	46505316 ps
T78	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3629066899	Jul 01 10:44:53 AM PDT 24	Jul 01 10:44:54 AM PDT 24	44032914 ps
T106	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1413821500	Jul 01 10:44:08 AM PDT 24	Jul 01 10:44:11 AM PDT 24	66488964 ps
T67	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1719104327	Jul 01 10:44:30 AM PDT 24	Jul 01 10:44:32 AM PDT 24	76723060 ps
T107	/workspace/coverage/cover_reg_top/26.i2c_intr_test.3540822544	Jul 01 10:44:31 AM PDT 24	Jul 01 10:44:32 AM PDT 24	46869191 ps
T108	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2143746638	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	38643543 ps
T109	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.66328800	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:13 AM PDT 24	24847733 ps
T35	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3034444750	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:24 AM PDT 24	31403697 ps
T110	/workspace/coverage/cover_reg_top/46.i2c_intr_test.559746037	Jul 01 10:44:47 AM PDT 24	Jul 01 10:44:48 AM PDT 24	28646579 ps
T36	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1462808533	Jul 01 10:44:36 AM PDT 24	Jul 01 10:44:39 AM PDT 24	20021347 ps
T56	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.74761295	Jul 01 10:44:31 AM PDT 24	Jul 01 10:44:33 AM PDT 24	84651059 ps
T37	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1589021098	Jul 01 10:44:04 AM PDT 24	Jul 01 10:44:06 AM PDT 24	17617323 ps
T111	/workspace/coverage/cover_reg_top/21.i2c_intr_test.1542151025	Jul 01 10:44:47 AM PDT 24	Jul 01 10:44:48 AM PDT 24	18099347 ps
T112	/workspace/coverage/cover_reg_top/31.i2c_intr_test.3419815321	Jul 01 10:44:44 AM PDT 24	Jul 01 10:44:45 AM PDT 24	45799901 ps
T113	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2947051353	Jul 01 10:44:39 AM PDT 24	Jul 01 10:44:51 AM PDT 24	32378385 ps
T114	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3302859773	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	44651414 ps
T115	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1382573355	Jul 01 10:44:37 AM PDT 24	Jul 01 10:44:40 AM PDT 24	110895923 ps
T116	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1681881009	Jul 01 10:44:18 AM PDT 24	Jul 01 10:44:20 AM PDT 24	132591884 ps
T68	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1485195088	Jul 01 10:44:08 AM PDT 24	Jul 01 10:44:10 AM PDT 24	20553450 ps
T117	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3837727418	Jul 01 10:44:43 AM PDT 24	Jul 01 10:44:45 AM PDT 24	63223421 ps
T79	/workspace/coverage/cover_reg_top/1.i2c_intr_test.2905000109	Jul 01 10:44:08 AM PDT 24	Jul 01 10:44:10 AM PDT 24	60850142 ps
T69	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1040547848	Jul 01 10:43:52 AM PDT 24	Jul 01 10:43:54 AM PDT 24	19849209 ps
T38	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2797995097	Jul 01 10:44:39 AM PDT 24	Jul 01 10:44:41 AM PDT 24	17561161 ps
T39	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.473579358	Jul 01 10:44:27 AM PDT 24	Jul 01 10:44:29 AM PDT 24	38210985 ps
T118	/workspace/coverage/cover_reg_top/22.i2c_intr_test.3279830095	Jul 01 10:44:27 AM PDT 24	Jul 01 10:44:28 AM PDT 24	42303580 ps
T65	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4140500856	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:30 AM PDT 24	319562087 ps
T66	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.148553858	Jul 01 10:44:48 AM PDT 24	Jul 01 10:44:50 AM PDT 24	162542282 ps
T119	/workspace/coverage/cover_reg_top/33.i2c_intr_test.62390587	Jul 01 10:44:25 AM PDT 24	Jul 01 10:44:27 AM PDT 24	51130430 ps
T120	/workspace/coverage/cover_reg_top/6.i2c_intr_test.226269427	Jul 01 10:44:11 AM PDT 24	Jul 01 10:44:12 AM PDT 24	26743402 ps
T57	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.863086704	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:20 AM PDT 24	259649237 ps
T80	/workspace/coverage/cover_reg_top/28.i2c_intr_test.535939874	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:27 AM PDT 24	82772491 ps
T121	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3243818891	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:19 AM PDT 24	30323567 ps
T122	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3008551546	Jul 01 10:44:42 AM PDT 24	Jul 01 10:44:44 AM PDT 24	1045560797 ps
T123	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2437122843	Jul 01 10:44:35 AM PDT 24	Jul 01 10:44:37 AM PDT 24	28202787 ps
T64	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1871637236	Jul 01 10:44:22 AM PDT 24	Jul 01 10:44:25 AM PDT 24	133670959 ps
T124	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3245194061	Jul 01 10:44:36 AM PDT 24	Jul 01 10:44:39 AM PDT 24	53083897 ps
T125	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3415013538	Jul 01 10:44:08 AM PDT 24	Jul 01 10:44:10 AM PDT 24	19199643 ps
T126	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.61904248	Jul 01 10:44:12 AM PDT 24	Jul 01 10:44:14 AM PDT 24	35138814 ps
T127	/workspace/coverage/cover_reg_top/3.i2c_intr_test.543428941	Jul 01 10:44:30 AM PDT 24	Jul 01 10:44:32 AM PDT 24	46875387 ps
T128	/workspace/coverage/cover_reg_top/0.i2c_intr_test.864030547	Jul 01 10:43:52 AM PDT 24	Jul 01 10:43:54 AM PDT 24	25446970 ps
T129	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3807593942	Jul 01 10:44:43 AM PDT 24	Jul 01 10:44:45 AM PDT 24	163506279 ps
T42	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3784311874	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:21 AM PDT 24	29586765 ps
T130	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4003552204	Jul 01 10:44:19 AM PDT 24	Jul 01 10:44:21 AM PDT 24	39314337 ps
T131	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1771912083	Jul 01 10:44:10 AM PDT 24	Jul 01 10:44:17 AM PDT 24	521902983 ps
T132	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.628036777	Jul 01 10:44:48 AM PDT 24	Jul 01 10:44:50 AM PDT 24	31743760 ps
T133	/workspace/coverage/cover_reg_top/37.i2c_intr_test.832708443	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:25 AM PDT 24	28109940 ps
T134	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2046148420	Jul 01 10:44:46 AM PDT 24	Jul 01 10:44:47 AM PDT 24	35992630 ps
T135	/workspace/coverage/cover_reg_top/47.i2c_intr_test.393713558	Jul 01 10:44:24 AM PDT 24	Jul 01 10:44:25 AM PDT 24	34790998 ps
T40	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.2957697669	Jul 01 10:44:49 AM PDT 24	Jul 01 10:44:50 AM PDT 24	44504862 ps
T136	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.212089695	Jul 01 10:44:19 AM PDT 24	Jul 01 10:44:22 AM PDT 24	157199770 ps
T137	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.966943604	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:25 AM PDT 24	31799869 ps
T138	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3218453804	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	16366549 ps
T139	/workspace/coverage/cover_reg_top/25.i2c_intr_test.3701121646	Jul 01 10:44:27 AM PDT 24	Jul 01 10:44:28 AM PDT 24	44082189 ps
T140	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4020388257	Jul 01 10:44:18 AM PDT 24	Jul 01 10:44:19 AM PDT 24	142933475 ps
T141	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.688853104	Jul 01 10:44:21 AM PDT 24	Jul 01 10:44:24 AM PDT 24	136981905 ps
T142	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1401599523	Jul 01 10:44:03 AM PDT 24	Jul 01 10:44:04 AM PDT 24	36153641 ps
T143	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.995030235	Jul 01 10:44:11 AM PDT 24	Jul 01 10:44:14 AM PDT 24	163213487 ps
T144	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1162919190	Jul 01 10:44:45 AM PDT 24	Jul 01 10:44:47 AM PDT 24	136270735 ps
T145	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1053022010	Jul 01 10:44:31 AM PDT 24	Jul 01 10:44:34 AM PDT 24	157765868 ps
T41	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2988605425	Jul 01 10:44:06 AM PDT 24	Jul 01 10:44:09 AM PDT 24	111108530 ps
T146	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2924023431	Jul 01 10:44:35 AM PDT 24	Jul 01 10:44:37 AM PDT 24	149924109 ps
T147	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1640423235	Jul 01 10:44:26 AM PDT 24	Jul 01 10:44:28 AM PDT 24	28491373 ps
T148	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1685841320	Jul 01 10:44:47 AM PDT 24	Jul 01 10:44:49 AM PDT 24	29689875 ps
T149	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.637583586	Jul 01 10:44:09 AM PDT 24	Jul 01 10:44:12 AM PDT 24	49874562 ps
T150	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2545345744	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:22 AM PDT 24	53134839 ps
T151	/workspace/coverage/cover_reg_top/48.i2c_intr_test.3632758250	Jul 01 10:44:24 AM PDT 24	Jul 01 10:44:30 AM PDT 24	65279930 ps
T70	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3851491858	Jul 01 10:44:17 AM PDT 24	Jul 01 10:44:18 AM PDT 24	50440935 ps
T55	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1956840914	Jul 01 10:44:22 AM PDT 24	Jul 01 10:44:24 AM PDT 24	239020539 ps
T152	/workspace/coverage/cover_reg_top/36.i2c_intr_test.224522195	Jul 01 10:44:43 AM PDT 24	Jul 01 10:44:55 AM PDT 24	18440910 ps
T153	/workspace/coverage/cover_reg_top/16.i2c_intr_test.2549300699	Jul 01 10:44:24 AM PDT 24	Jul 01 10:44:25 AM PDT 24	17591927 ps
T154	/workspace/coverage/cover_reg_top/7.i2c_intr_test.3845219491	Jul 01 10:44:23 AM PDT 24	Jul 01 10:44:24 AM PDT 24	37147637 ps
T155	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2905210851	Jul 01 10:44:46 AM PDT 24	Jul 01 10:44:47 AM PDT 24	27911995 ps
T156	/workspace/coverage/cover_reg_top/13.i2c_intr_test.3367084188	Jul 01 10:44:20 AM PDT 24	Jul 01 10:44:21 AM PDT 24	42366343 ps
T157	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2045337015	Jul 01 10:44:46 AM PDT 24	Jul 01 10:44:48 AM PDT 24	33460228 ps
T158	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1242542607	Jul 01 10:44:15 AM PDT 24	Jul 01 10:44:16 AM PDT 24	99103849 ps
T43	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1313408334	Jul 01 10:44:15 AM PDT 24	Jul 01 10:44:16 AM PDT 24	58542896 ps
T159	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.447693548	Jul 01 10:44:13 AM PDT 24	Jul 01 10:44:15 AM PDT 24	47485481 ps
T160	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1814052409	Jul 01 10:44:39 AM PDT 24	Jul 01 10:44:40 AM PDT 24	19599689 ps

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.89376651
Short name	T5
Test name
Test status
Simulation time	708188971 ps
CPU time	1.59 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204484 kb
Host	smart-d9d14df8-4344-4df5-a4bc-2f627aeea505
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89376651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.89376651
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.825955524
Short name	T11
Test name
Test status
Simulation time	29372578 ps
CPU time	0.69 seconds
Started	Jul 01 10:44:45 AM PDT 24
Finished	Jul 01 10:44:46 AM PDT 24
Peak memory	204328 kb
Host	smart-ec266133-9da4-497b-b325-7ab125af9e0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825955524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.825955524
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2498428869
Short name	T6
Test name
Test status
Simulation time	209715526 ps
CPU time	2.12 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204456 kb
Host	smart-b1d36a46-fdd8-4153-a325-09750794efd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498428869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2498428869
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2690820685
Short name	T27
Test name
Test status
Simulation time	31405680 ps
CPU time	0.79 seconds
Started	Jul 01 10:44:09 AM PDT 24
Finished	Jul 01 10:44:11 AM PDT 24
Peak memory	204364 kb
Host	smart-24e7ae30-4c2f-4be3-b1f7-85cda5534236
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690820685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2690820685
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1208923239
Short name	T9
Test name
Test status
Simulation time	18910630 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204312 kb
Host	smart-0f0da656-4588-408f-9498-91d7e5527ab3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208923239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1208923239
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4256732467
Short name	T17
Test name
Test status
Simulation time	21459589 ps
CPU time	0.86 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204364 kb
Host	smart-f0fd715b-1188-4937-b8f1-4b01f0b877dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256732467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.4256732467
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2143746638
Short name	T108
Test name
Test status
Simulation time	38643543 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204320 kb
Host	smart-15506bb6-3a68-4528-b336-38db4fa6e1c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143746638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2143746638
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4065306150
Short name	T2
Test name
Test status
Simulation time	649565984 ps
CPU time	2.54 seconds
Started	Jul 01 10:43:57 AM PDT 24
Finished	Jul 01 10:44:04 AM PDT 24
Peak memory	204480 kb
Host	smart-414c9f85-ee63-4982-9b59-5a6dbea57069
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065306150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.4065306150
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1522438606
Short name	T72
Test name
Test status
Simulation time	61535433 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:21 AM PDT 24
Finished	Jul 01 10:44:23 AM PDT 24
Peak memory	204260 kb
Host	smart-335b154e-3b1b-4d7e-8124-9c1934b518c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522438606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1522438606
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1598862284
Short name	T14
Test name
Test status
Simulation time	29689793 ps
CPU time	1.16 seconds
Started	Jul 01 10:44:18 AM PDT 24
Finished	Jul 01 10:44:20 AM PDT 24
Peak memory	204532 kb
Host	smart-6868da45-97ad-4935-942e-31d8d622a6e0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598862284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.1598862284
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.535939874
Short name	T80
Test name
Test status
Simulation time	82772491 ps
CPU time	0.65 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204296 kb
Host	smart-e4ca6caf-2890-4d20-a581-ecde94c3ef0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535939874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.535939874
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2729090944
Short name	T47
Test name
Test status
Simulation time	443810543 ps
CPU time	1.76 seconds
Started	Jul 01 10:44:41 AM PDT 24
Finished	Jul 01 10:44:43 AM PDT 24
Peak memory	204548 kb
Host	smart-510e32e1-7cf6-4b90-8c58-4649f719faa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729090944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2729090944
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1040547848
Short name	T69
Test name
Test status
Simulation time	19849209 ps
CPU time	0.74 seconds
Started	Jul 01 10:43:52 AM PDT 24
Finished	Jul 01 10:43:54 AM PDT 24
Peak memory	204280 kb
Host	smart-4c36c0cc-fd29-4df1-837e-f0f637257431
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040547848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1040547848
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1485195088
Short name	T68
Test name
Test status
Simulation time	20553450 ps
CPU time	0.96 seconds
Started	Jul 01 10:44:08 AM PDT 24
Finished	Jul 01 10:44:10 AM PDT 24
Peak memory	204408 kb
Host	smart-a3191319-7369-46e5-8228-4396585f53b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485195088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.1485195088
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.2682925980
Short name	T77
Test name
Test status
Simulation time	43885265 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204344 kb
Host	smart-197bcdac-213a-4279-ad8d-665da8bbd643
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682925980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2682925980
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2878472811
Short name	T33
Test name
Test status
Simulation time	79757491 ps
CPU time	1.12 seconds
Started	Jul 01 10:44:07 AM PDT 24
Finished	Jul 01 10:44:09 AM PDT 24
Peak memory	204456 kb
Host	smart-d8ba45be-84eb-4b16-ae13-c7f854b03e87
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878472811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.2878472811
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.863086704
Short name	T57
Test name
Test status
Simulation time	259649237 ps
CPU time	2.15 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:20 AM PDT 24
Peak memory	204376 kb
Host	smart-7c43f35e-a47e-4da1-a673-c21f3591d786
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863086704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.863086704
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1720079837
Short name	T90
Test name
Test status
Simulation time	402038600 ps
CPU time	2.56 seconds
Started	Jul 01 10:44:18 AM PDT 24
Finished	Jul 01 10:44:21 AM PDT 24
Peak memory	204488 kb
Host	smart-f84fd7ff-58ba-430d-9490-3756500e4a74
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720079837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1720079837
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3468341036
Short name	T22
Test name
Test status
Simulation time	87967913 ps
CPU time	2.33 seconds
Started	Jul 01 10:44:16 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204476 kb
Host	smart-9e69e04b-f2c8-4290-8181-16d36d8eefc9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468341036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3468341036
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2989281346
Short name	T58
Test name
Test status
Simulation time	306707447 ps
CPU time	2.24 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:26 AM PDT 24
Peak memory	204492 kb
Host	smart-8f8928a2-0320-4ba7-b49a-9542742993a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989281346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2989281346
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4140500856
Short name	T65
Test name
Test status
Simulation time	319562087 ps
CPU time	2.48 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:30 AM PDT 24
Peak memory	204468 kb
Host	smart-ec17f052-e973-40e4-a34f-8c1472ce1b8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140500856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4140500856
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.212089695
Short name	T136
Test name
Test status
Simulation time	157199770 ps
CPU time	2.25 seconds
Started	Jul 01 10:44:19 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204380 kb
Host	smart-abb4f8af-b1b2-415f-b91b-0f0f5dfb4e8a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212089695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.212089695
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1055360388
Short name	T7
Test name
Test status
Simulation time	76183420 ps
CPU time	2.93 seconds
Started	Jul 01 10:44:16 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204468 kb
Host	smart-091740a0-9f96-4042-bd31-a4cf97764d80
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055360388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1055360388
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3426919527
Short name	T95
Test name
Test status
Simulation time	66699167 ps
CPU time	0.96 seconds
Started	Jul 01 10:43:58 AM PDT 24
Finished	Jul 01 10:44:03 AM PDT 24
Peak memory	204436 kb
Host	smart-2bbeed43-f5a5-4d40-adfe-d139b7725e03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426919527 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3426919527
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1401599523
Short name	T142
Test name
Test status
Simulation time	36153641 ps
CPU time	0.74 seconds
Started	Jul 01 10:44:03 AM PDT 24
Finished	Jul 01 10:44:04 AM PDT 24
Peak memory	204364 kb
Host	smart-d5a0090d-04ce-428b-ab7d-0a3afeb93973
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401599523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1401599523
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.864030547
Short name	T128
Test name
Test status
Simulation time	25446970 ps
CPU time	0.67 seconds
Started	Jul 01 10:43:52 AM PDT 24
Finished	Jul 01 10:43:54 AM PDT 24
Peak memory	204280 kb
Host	smart-922bb2b9-0379-4d5b-8abc-912ba5928522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864030547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.864030547
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3520519819
Short name	T93
Test name
Test status
Simulation time	34150195 ps
CPU time	0.91 seconds
Started	Jul 01 10:44:37 AM PDT 24
Finished	Jul 01 10:44:39 AM PDT 24
Peak memory	204328 kb
Host	smart-c6fea6ce-8207-4ca6-af51-4127a152cdf6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520519819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.3520519819
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.770380582
Short name	T60
Test name
Test status
Simulation time	51616994 ps
CPU time	1.45 seconds
Started	Jul 01 10:44:02 AM PDT 24
Finished	Jul 01 10:44:04 AM PDT 24
Peak memory	204544 kb
Host	smart-3749f27f-3774-4b70-8db8-194c2b348c22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770380582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.770380582
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.767430290
Short name	T1
Test name
Test status
Simulation time	132876421 ps
CPU time	1.4 seconds
Started	Jul 01 10:44:22 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204412 kb
Host	smart-c0eea618-bc09-4a92-8d25-fe475de0c3fc
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767430290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.767430290
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3851491858
Short name	T70
Test name
Test status
Simulation time	50440935 ps
CPU time	0.71 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:18 AM PDT 24
Peak memory	204380 kb
Host	smart-a639d5ae-8d9e-4bd1-9aa6-145c572ddc5b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851491858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3851491858
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4003552204
Short name	T130
Test name
Test status
Simulation time	39314337 ps
CPU time	1.04 seconds
Started	Jul 01 10:44:19 AM PDT 24
Finished	Jul 01 10:44:21 AM PDT 24
Peak memory	204500 kb
Host	smart-f653f38e-b404-4d54-ab75-06945dfeadbc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003552204 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4003552204
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1589021098
Short name	T37
Test name
Test status
Simulation time	17617323 ps
CPU time	0.72 seconds
Started	Jul 01 10:44:04 AM PDT 24
Finished	Jul 01 10:44:06 AM PDT 24
Peak memory	204332 kb
Host	smart-287a51da-7112-491b-84e5-990853664fb5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589021098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1589021098
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.2905000109
Short name	T79
Test name
Test status
Simulation time	60850142 ps
CPU time	0.72 seconds
Started	Jul 01 10:44:08 AM PDT 24
Finished	Jul 01 10:44:10 AM PDT 24
Peak memory	204308 kb
Host	smart-053cacf7-a865-439f-821a-736b5b6b10d5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905000109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2905000109
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3619673964
Short name	T94
Test name
Test status
Simulation time	157794995 ps
CPU time	1.66 seconds
Started	Jul 01 10:44:09 AM PDT 24
Finished	Jul 01 10:44:12 AM PDT 24
Peak memory	204588 kb
Host	smart-ca34b587-2d1c-4b60-b5b9-aba527830ee8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619673964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3619673964
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2046148420
Short name	T134
Test name
Test status
Simulation time	35992630 ps
CPU time	0.91 seconds
Started	Jul 01 10:44:46 AM PDT 24
Finished	Jul 01 10:44:47 AM PDT 24
Peak memory	204484 kb
Host	smart-0429e7fc-9186-4fd7-8adc-c3ae8d158e5a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046148420 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2046148420
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1823762282
Short name	T87
Test name
Test status
Simulation time	323580055 ps
CPU time	0.77 seconds
Started	Jul 01 10:44:40 AM PDT 24
Finished	Jul 01 10:44:42 AM PDT 24
Peak memory	204276 kb
Host	smart-1f5f1af0-4cb0-41f5-8146-ced2d84a3bd0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823762282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1823762282
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1814052409
Short name	T160
Test name
Test status
Simulation time	19599689 ps
CPU time	0.71 seconds
Started	Jul 01 10:44:39 AM PDT 24
Finished	Jul 01 10:44:40 AM PDT 24
Peak memory	204324 kb
Host	smart-3d1963de-0e2b-463b-b324-ab3ef4952202
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814052409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1814052409
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2452480447
Short name	T46
Test name
Test status
Simulation time	68286884 ps
CPU time	0.89 seconds
Started	Jul 01 10:44:16 AM PDT 24
Finished	Jul 01 10:44:18 AM PDT 24
Peak memory	204320 kb
Host	smart-f17a4811-c0b8-44ab-a525-1bbc47076e84
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452480447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.2452480447
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1176827544
Short name	T19
Test name
Test status
Simulation time	463774410 ps
CPU time	2.63 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:15 AM PDT 24
Peak memory	204588 kb
Host	smart-297a6718-47ed-4b3e-9217-a1d94773674b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176827544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1176827544
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1469170119
Short name	T96
Test name
Test status
Simulation time	47287543 ps
CPU time	0.8 seconds
Started	Jul 01 10:44:21 AM PDT 24
Finished	Jul 01 10:44:23 AM PDT 24
Peak memory	204468 kb
Host	smart-5c49de31-bb43-49a1-b6a0-2ad8a4cfd64d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469170119 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1469170119
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4020388257
Short name	T140
Test name
Test status
Simulation time	142933475 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:18 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204352 kb
Host	smart-bdf60223-ecd8-4625-9a45-8935a4cfc996
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020388257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.4020388257
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1392118853
Short name	T103
Test name
Test status
Simulation time	52162511 ps
CPU time	0.75 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:18 AM PDT 24
Peak memory	204552 kb
Host	smart-53d1f830-a20e-4da8-a4ae-ceddbbc3e68d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392118853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1392118853
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3517054102
Short name	T101
Test name
Test status
Simulation time	23138821 ps
CPU time	0.88 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:18 AM PDT 24
Peak memory	204412 kb
Host	smart-dee74fd2-89de-4348-bee7-dca27fa954ac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517054102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.3517054102
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1753884885
Short name	T25
Test name
Test status
Simulation time	563358595 ps
CPU time	2.62 seconds
Started	Jul 01 10:44:50 AM PDT 24
Finished	Jul 01 10:44:53 AM PDT 24
Peak memory	204436 kb
Host	smart-b938e7d4-7123-4aeb-83c8-6071ea0a941f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753884885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1753884885
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1053022010
Short name	T145
Test name
Test status
Simulation time	157765868 ps
CPU time	2.27 seconds
Started	Jul 01 10:44:31 AM PDT 24
Finished	Jul 01 10:44:34 AM PDT 24
Peak memory	204388 kb
Host	smart-ce09e0fc-6df3-4238-9391-6297dcfa63cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053022010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1053022010
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3050796071
Short name	T98
Test name
Test status
Simulation time	52339105 ps
CPU time	0.85 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204452 kb
Host	smart-3250f870-a959-4c89-94bb-c32b7c678491
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050796071 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3050796071
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.4120937924
Short name	T44
Test name
Test status
Simulation time	24360832 ps
CPU time	0.77 seconds
Started	Jul 01 10:44:19 AM PDT 24
Finished	Jul 01 10:44:20 AM PDT 24
Peak memory	204412 kb
Host	smart-1a4aae79-80b3-47c9-944f-fe61b2090612
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120937924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.4120937924
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3302859773
Short name	T114
Test name
Test status
Simulation time	44651414 ps
CPU time	0.68 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204320 kb
Host	smart-8e744ea0-a43e-4d46-917b-88b638be0687
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302859773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3302859773
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.688853104
Short name	T141
Test name
Test status
Simulation time	136981905 ps
CPU time	1.91 seconds
Started	Jul 01 10:44:21 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204600 kb
Host	smart-47f706d2-55fa-49c0-a740-f3023227fffc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688853104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.688853104
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1206426021
Short name	T8
Test name
Test status
Simulation time	47268147 ps
CPU time	0.86 seconds
Started	Jul 01 10:44:35 AM PDT 24
Finished	Jul 01 10:44:37 AM PDT 24
Peak memory	204332 kb
Host	smart-59d90416-ff03-48e6-b102-13ba424767a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206426021 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1206426021
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.473579358
Short name	T39
Test name
Test status
Simulation time	38210985 ps
CPU time	0.74 seconds
Started	Jul 01 10:44:27 AM PDT 24
Finished	Jul 01 10:44:29 AM PDT 24
Peak memory	204396 kb
Host	smart-d402cb0b-4c6a-478a-9541-44a192053d45
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473579358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.473579358
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.3367084188
Short name	T156
Test name
Test status
Simulation time	42366343 ps
CPU time	0.68 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:21 AM PDT 24
Peak memory	204384 kb
Host	smart-13d643ec-e85b-4487-9d79-01d9a6c0fabb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367084188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3367084188
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3689365022
Short name	T91
Test name
Test status
Simulation time	100149927 ps
CPU time	1.18 seconds
Started	Jul 01 10:44:45 AM PDT 24
Finished	Jul 01 10:44:47 AM PDT 24
Peak memory	204560 kb
Host	smart-70d8f002-cded-45fd-ad49-01b7f230bee6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689365022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3689365022
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2898009726
Short name	T18
Test name
Test status
Simulation time	42152893 ps
CPU time	1.24 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204616 kb
Host	smart-3c15c3ac-0a55-4302-aa5a-297a204dcaba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898009726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2898009726
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1578565600
Short name	T63
Test name
Test status
Simulation time	95822582 ps
CPU time	1.58 seconds
Started	Jul 01 10:44:32 AM PDT 24
Finished	Jul 01 10:44:34 AM PDT 24
Peak memory	204524 kb
Host	smart-4368df66-770c-444f-9c32-1bdcb677ca9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578565600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1578565600
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1685841320
Short name	T148
Test name
Test status
Simulation time	29689875 ps
CPU time	1.35 seconds
Started	Jul 01 10:44:47 AM PDT 24
Finished	Jul 01 10:44:49 AM PDT 24
Peak memory	212808 kb
Host	smart-48a4a166-751b-4ed7-9368-d2379996ad4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685841320 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1685841320
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3121400829
Short name	T32
Test name
Test status
Simulation time	23187483 ps
CPU time	0.73 seconds
Started	Jul 01 10:44:27 AM PDT 24
Finished	Jul 01 10:44:29 AM PDT 24
Peak memory	204404 kb
Host	smart-5700da1a-f601-4f6d-846e-bd48a912ba25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121400829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3121400829
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.874534238
Short name	T74
Test name
Test status
Simulation time	28475728 ps
CPU time	0.69 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204408 kb
Host	smart-c93b4d0b-6e89-408f-b0ae-126661cd8bd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874534238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.874534238
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1956840914
Short name	T55
Test name
Test status
Simulation time	239020539 ps
CPU time	1.18 seconds
Started	Jul 01 10:44:22 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204424 kb
Host	smart-be58d8b1-95e4-487d-a63e-50ebeb7f45df
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956840914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.1956840914
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3837727418
Short name	T117
Test name
Test status
Simulation time	63223421 ps
CPU time	1.71 seconds
Started	Jul 01 10:44:43 AM PDT 24
Finished	Jul 01 10:44:45 AM PDT 24
Peak memory	204596 kb
Host	smart-e8194911-a042-4aa7-aa1a-9dc6bfa79b26
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837727418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3837727418
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1796605465
Short name	T50
Test name
Test status
Simulation time	466064114 ps
CPU time	1.7 seconds
Started	Jul 01 10:44:16 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204544 kb
Host	smart-d50d7fb5-b137-4a67-877d-009e7359f603
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796605465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1796605465
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.206029090
Short name	T21
Test name
Test status
Simulation time	26104128 ps
CPU time	0.91 seconds
Started	Jul 01 10:44:22 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204440 kb
Host	smart-5d60eabb-fbf3-45fb-bbc8-49474ad1af46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206029090 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.206029090
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.447693548
Short name	T159
Test name
Test status
Simulation time	47485481 ps
CPU time	0.81 seconds
Started	Jul 01 10:44:13 AM PDT 24
Finished	Jul 01 10:44:15 AM PDT 24
Peak memory	204428 kb
Host	smart-9766535c-e053-4674-86d8-5819a4be3989
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447693548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.447693548
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1178804397
Short name	T76
Test name
Test status
Simulation time	21478836 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204288 kb
Host	smart-fb06a354-9a24-4363-91c2-f020e7e20897
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178804397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1178804397
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1242542607
Short name	T158
Test name
Test status
Simulation time	99103849 ps
CPU time	0.78 seconds
Started	Jul 01 10:44:15 AM PDT 24
Finished	Jul 01 10:44:16 AM PDT 24
Peak memory	204344 kb
Host	smart-ca327925-ce0b-41c1-9c05-3918e9a103b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242542607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1242542607
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.995030235
Short name	T143
Test name
Test status
Simulation time	163213487 ps
CPU time	2.42 seconds
Started	Jul 01 10:44:11 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204608 kb
Host	smart-e4848361-8a1d-40c8-9598-977b28f1c3ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995030235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.995030235
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2437122843
Short name	T123
Test name
Test status
Simulation time	28202787 ps
CPU time	1.2 seconds
Started	Jul 01 10:44:35 AM PDT 24
Finished	Jul 01 10:44:37 AM PDT 24
Peak memory	212748 kb
Host	smart-0267f193-add9-493b-8dba-9e8c5d4b1b44
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437122843 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2437122843
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1462808533
Short name	T36
Test name
Test status
Simulation time	20021347 ps
CPU time	0.8 seconds
Started	Jul 01 10:44:36 AM PDT 24
Finished	Jul 01 10:44:39 AM PDT 24
Peak memory	204444 kb
Host	smart-4bb83054-1f80-4886-b888-7c1291bf598c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462808533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1462808533
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.2549300699
Short name	T153
Test name
Test status
Simulation time	17591927 ps
CPU time	0.74 seconds
Started	Jul 01 10:44:24 AM PDT 24
Finished	Jul 01 10:44:25 AM PDT 24
Peak memory	204328 kb
Host	smart-43354c83-2356-4096-9c99-81b14cb33f41
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549300699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2549300699
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3464737892
Short name	T31
Test name
Test status
Simulation time	66809252 ps
CPU time	0.85 seconds
Started	Jul 01 10:44:33 AM PDT 24
Finished	Jul 01 10:44:34 AM PDT 24
Peak memory	204388 kb
Host	smart-bf345add-b911-494d-91bc-c88be70f388b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464737892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.3464737892
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.966943604
Short name	T137
Test name
Test status
Simulation time	31799869 ps
CPU time	0.95 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:25 AM PDT 24
Peak memory	204392 kb
Host	smart-bd04c724-a3a7-47b1-b1a3-bd69eb6a6c13
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966943604 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.966943604
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2335971619
Short name	T3
Test name
Test status
Simulation time	22731493 ps
CPU time	0.82 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204420 kb
Host	smart-3bbbf303-78dd-4ebd-ac24-25c4d157153a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335971619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2335971619
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2988103156
Short name	T48
Test name
Test status
Simulation time	375254365 ps
CPU time	0.92 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204408 kb
Host	smart-e7c7be0b-80ed-4231-9a09-550a18b7d216
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988103156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.2988103156
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1772872459
Short name	T92
Test name
Test status
Simulation time	633038724 ps
CPU time	1.51 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204528 kb
Host	smart-168d55d3-859f-4483-aef2-d7dd5f5d51fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772872459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1772872459
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2924023431
Short name	T146
Test name
Test status
Simulation time	149924109 ps
CPU time	0.88 seconds
Started	Jul 01 10:44:35 AM PDT 24
Finished	Jul 01 10:44:37 AM PDT 24
Peak memory	204404 kb
Host	smart-8b3bb717-0f2e-407f-9291-eca7fd4d7be3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924023431 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2924023431
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3784311874
Short name	T42
Test name
Test status
Simulation time	29586765 ps
CPU time	0.81 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:21 AM PDT 24
Peak memory	204384 kb
Host	smart-96b7347d-99f0-46e5-b542-bfd16c97f4d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784311874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3784311874
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.1783534998
Short name	T82
Test name
Test status
Simulation time	87415555 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:47 AM PDT 24
Finished	Jul 01 10:44:48 AM PDT 24
Peak memory	204348 kb
Host	smart-f525c5cf-7fb0-4348-b09a-8aa60be59c34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783534998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1783534998
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2947051353
Short name	T113
Test name
Test status
Simulation time	32378385 ps
CPU time	1.05 seconds
Started	Jul 01 10:44:39 AM PDT 24
Finished	Jul 01 10:44:51 AM PDT 24
Peak memory	204516 kb
Host	smart-5eb7c023-4c1d-4c68-8777-c4639b7c6782
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947051353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2947051353
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.628036777
Short name	T132
Test name
Test status
Simulation time	31743760 ps
CPU time	1.57 seconds
Started	Jul 01 10:44:48 AM PDT 24
Finished	Jul 01 10:44:50 AM PDT 24
Peak memory	212672 kb
Host	smart-d39b295c-7de7-432d-835e-2261f6d1d1d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628036777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.628036777
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1162919190
Short name	T144
Test name
Test status
Simulation time	136270735 ps
CPU time	1 seconds
Started	Jul 01 10:44:45 AM PDT 24
Finished	Jul 01 10:44:47 AM PDT 24
Peak memory	204480 kb
Host	smart-e0b4b117-e06a-4123-afd3-e17e7e8bb1bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162919190 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1162919190
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2797995097
Short name	T38
Test name
Test status
Simulation time	17561161 ps
CPU time	0.73 seconds
Started	Jul 01 10:44:39 AM PDT 24
Finished	Jul 01 10:44:41 AM PDT 24
Peak memory	204368 kb
Host	smart-30e12eab-2307-4407-bf20-a39d00c1f52c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797995097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2797995097
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.1661064046
Short name	T83
Test name
Test status
Simulation time	28729364 ps
CPU time	0.64 seconds
Started	Jul 01 10:44:49 AM PDT 24
Finished	Jul 01 10:44:50 AM PDT 24
Peak memory	204300 kb
Host	smart-fc8e968c-7608-4035-9703-e946ffc51b99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661064046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1661064046
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3921097415
Short name	T51
Test name
Test status
Simulation time	99484631 ps
CPU time	0.97 seconds
Started	Jul 01 10:44:44 AM PDT 24
Finished	Jul 01 10:44:46 AM PDT 24
Peak memory	204400 kb
Host	smart-27fe37ce-83fd-4ca9-88a2-718040a3366b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921097415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.3921097415
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3008551546
Short name	T122
Test name
Test status
Simulation time	1045560797 ps
CPU time	1.64 seconds
Started	Jul 01 10:44:42 AM PDT 24
Finished	Jul 01 10:44:44 AM PDT 24
Peak memory	204556 kb
Host	smart-716f278f-cc7b-4b2f-b3eb-6f9dd7016d32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008551546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3008551546
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1681881009
Short name	T116
Test name
Test status
Simulation time	132591884 ps
CPU time	1.38 seconds
Started	Jul 01 10:44:18 AM PDT 24
Finished	Jul 01 10:44:20 AM PDT 24
Peak memory	204464 kb
Host	smart-3acdbe83-cddc-4ea0-83ca-31e00211719b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681881009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1681881009
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3448391427
Short name	T30
Test name
Test status
Simulation time	138515580 ps
CPU time	5.49 seconds
Started	Jul 01 10:43:59 AM PDT 24
Finished	Jul 01 10:44:07 AM PDT 24
Peak memory	204484 kb
Host	smart-b48e42ba-98c3-457d-87c2-499bff34495a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448391427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3448391427
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3034444750
Short name	T35
Test name
Test status
Simulation time	31403697 ps
CPU time	0.69 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204376 kb
Host	smart-dbcbf542-4ac0-4e80-bbd8-5c98bb5f794a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034444750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3034444750
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4111234949
Short name	T100
Test name
Test status
Simulation time	207158181 ps
CPU time	1.02 seconds
Started	Jul 01 10:44:11 AM PDT 24
Finished	Jul 01 10:44:12 AM PDT 24
Peak memory	204456 kb
Host	smart-5fdb0dda-0485-4d78-a33b-e240d577db5b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111234949 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4111234949
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2545345744
Short name	T150
Test name
Test status
Simulation time	53134839 ps
CPU time	0.65 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204264 kb
Host	smart-23d160fc-359b-4851-b0ed-c97ea702eb9e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545345744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2545345744
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3807391691
Short name	T13
Test name
Test status
Simulation time	14744990 ps
CPU time	0.66 seconds
Started	Jul 01 10:43:57 AM PDT 24
Finished	Jul 01 10:44:01 AM PDT 24
Peak memory	204280 kb
Host	smart-b6bed335-c80c-4acb-9a3f-013741e37a2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807391691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3807391691
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1719104327
Short name	T67
Test name
Test status
Simulation time	76723060 ps
CPU time	1.19 seconds
Started	Jul 01 10:44:30 AM PDT 24
Finished	Jul 01 10:44:32 AM PDT 24
Peak memory	204488 kb
Host	smart-65037c97-b867-4ac2-841f-25c852f9f847
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719104327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.1719104327
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1213854980
Short name	T104
Test name
Test status
Simulation time	430099485 ps
CPU time	2.79 seconds
Started	Jul 01 10:43:59 AM PDT 24
Finished	Jul 01 10:44:05 AM PDT 24
Peak memory	204476 kb
Host	smart-0941b0a9-39f0-4fbb-be6e-6c2fa6505416
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213854980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1213854980
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4283827262
Short name	T71
Test name
Test status
Simulation time	51252710 ps
CPU time	1.47 seconds
Started	Jul 01 10:43:58 AM PDT 24
Finished	Jul 01 10:44:03 AM PDT 24
Peak memory	204368 kb
Host	smart-cd43a692-43a5-4a48-8b7d-579a24180b7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283827262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.4283827262
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.1542151025
Short name	T111
Test name
Test status
Simulation time	18099347 ps
CPU time	0.65 seconds
Started	Jul 01 10:44:47 AM PDT 24
Finished	Jul 01 10:44:48 AM PDT 24
Peak memory	204180 kb
Host	smart-a39b4291-16be-4f35-b0c3-aacb19117304
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542151025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1542151025
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.3279830095
Short name	T118
Test name
Test status
Simulation time	42303580 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:27 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204300 kb
Host	smart-c3efc8dc-f325-4676-81cf-dbd180bd7a62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279830095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3279830095
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.2480720185
Short name	T88
Test name
Test status
Simulation time	15611735 ps
CPU time	0.74 seconds
Started	Jul 01 10:44:36 AM PDT 24
Finished	Jul 01 10:44:38 AM PDT 24
Peak memory	204312 kb
Host	smart-06bc96b4-b0ad-479c-9413-8e831992b6af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480720185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2480720185
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1640423235
Short name	T147
Test name
Test status
Simulation time	28491373 ps
CPU time	0.63 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204264 kb
Host	smart-636aec14-da67-48da-bde9-669326601052
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640423235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1640423235
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.3701121646
Short name	T139
Test name
Test status
Simulation time	44082189 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:27 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204300 kb
Host	smart-54be1bf2-d83e-44e9-ac1e-08f7a8a033bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701121646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3701121646
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.3540822544
Short name	T107
Test name
Test status
Simulation time	46869191 ps
CPU time	0.68 seconds
Started	Jul 01 10:44:31 AM PDT 24
Finished	Jul 01 10:44:32 AM PDT 24
Peak memory	204328 kb
Host	smart-fdef0c9c-ef63-402c-97c3-b2c37e9425cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540822544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3540822544
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3972185176
Short name	T105
Test name
Test status
Simulation time	46505316 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:35 AM PDT 24
Finished	Jul 01 10:44:37 AM PDT 24
Peak memory	204312 kb
Host	smart-03ac64dc-1773-4cab-bacb-3e5017d91d29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972185176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3972185176
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2988605425
Short name	T41
Test name
Test status
Simulation time	111108530 ps
CPU time	2.17 seconds
Started	Jul 01 10:44:06 AM PDT 24
Finished	Jul 01 10:44:09 AM PDT 24
Peak memory	204480 kb
Host	smart-2445242d-2a6d-447a-85b6-51004d5f09d0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988605425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2988605425
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1771912083
Short name	T131
Test name
Test status
Simulation time	521902983 ps
CPU time	5.53 seconds
Started	Jul 01 10:44:10 AM PDT 24
Finished	Jul 01 10:44:17 AM PDT 24
Peak memory	204376 kb
Host	smart-b436c0e7-f54a-4aa1-9593-5dd80bbacc43
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771912083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1771912083
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1313408334
Short name	T43
Test name
Test status
Simulation time	58542896 ps
CPU time	0.76 seconds
Started	Jul 01 10:44:15 AM PDT 24
Finished	Jul 01 10:44:16 AM PDT 24
Peak memory	204600 kb
Host	smart-fef3bd6b-add7-498c-bd51-ec03ceaba494
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313408334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1313408334
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3807593942
Short name	T129
Test name
Test status
Simulation time	163506279 ps
CPU time	0.84 seconds
Started	Jul 01 10:44:43 AM PDT 24
Finished	Jul 01 10:44:45 AM PDT 24
Peak memory	204476 kb
Host	smart-d895fc01-68dc-41a3-b434-f691825e27f9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807593942 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3807593942
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2747438744
Short name	T29
Test name
Test status
Simulation time	29948767 ps
CPU time	0.81 seconds
Started	Jul 01 10:44:21 AM PDT 24
Finished	Jul 01 10:44:23 AM PDT 24
Peak memory	204312 kb
Host	smart-ec6afbf6-f022-48d4-9812-4b6f60ad593d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747438744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2747438744
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.543428941
Short name	T127
Test name
Test status
Simulation time	46875387 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:30 AM PDT 24
Finished	Jul 01 10:44:32 AM PDT 24
Peak memory	204340 kb
Host	smart-3ef114f1-1350-4862-9e06-96de91c5bbcd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543428941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.543428941
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2366051050
Short name	T61
Test name
Test status
Simulation time	36054245 ps
CPU time	1.64 seconds
Started	Jul 01 10:44:05 AM PDT 24
Finished	Jul 01 10:44:08 AM PDT 24
Peak memory	204544 kb
Host	smart-7cac54e6-c16d-4967-a2de-7bff21bfd869
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366051050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2366051050
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2201077207
Short name	T49
Test name
Test status
Simulation time	623797503 ps
CPU time	2.69 seconds
Started	Jul 01 10:44:07 AM PDT 24
Finished	Jul 01 10:44:11 AM PDT 24
Peak memory	204548 kb
Host	smart-f743957e-3a28-443d-b0f2-e48498d02d83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201077207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2201077207
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.3113968310
Short name	T12
Test name
Test status
Simulation time	17883129 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:27 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204296 kb
Host	smart-413c657f-031d-4683-ad0f-a0f5653fd214
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113968310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3113968310
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.3419815321
Short name	T112
Test name
Test status
Simulation time	45799901 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:44 AM PDT 24
Finished	Jul 01 10:44:45 AM PDT 24
Peak memory	204320 kb
Host	smart-aea1ceb8-5452-4ea2-a293-40ff986e650f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419815321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3419815321
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.412937859
Short name	T73
Test name
Test status
Simulation time	31283723 ps
CPU time	0.63 seconds
Started	Jul 01 10:44:40 AM PDT 24
Finished	Jul 01 10:44:41 AM PDT 24
Peak memory	204208 kb
Host	smart-018cdb30-0a2a-4fc2-a108-46410d8afb82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412937859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.412937859
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.62390587
Short name	T119
Test name
Test status
Simulation time	51130430 ps
CPU time	0.64 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204292 kb
Host	smart-4a06369e-64d3-480f-b857-f8229640ba16
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62390587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.62390587
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.259435901
Short name	T86
Test name
Test status
Simulation time	36909657 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204296 kb
Host	smart-124a6df5-a349-44fc-8b63-10ba8603eece
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259435901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.259435901
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.3938629125
Short name	T52
Test name
Test status
Simulation time	119337997 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:41 AM PDT 24
Finished	Jul 01 10:44:43 AM PDT 24
Peak memory	204296 kb
Host	smart-aff45cb9-bd50-41f8-9de9-d29294bb0463
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938629125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3938629125
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.224522195
Short name	T152
Test name
Test status
Simulation time	18440910 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:43 AM PDT 24
Finished	Jul 01 10:44:55 AM PDT 24
Peak memory	204224 kb
Host	smart-d0050995-e9e0-4ddf-b126-1f04ddc54cea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224522195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.224522195
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.832708443
Short name	T133
Test name
Test status
Simulation time	28109940 ps
CPU time	0.65 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:25 AM PDT 24
Peak memory	204300 kb
Host	smart-97b84758-4c26-49d7-8762-6fe92113da8d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832708443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.832708443
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3970350774
Short name	T85
Test name
Test status
Simulation time	28069009 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204296 kb
Host	smart-d0293329-f93a-4590-b542-1c037a484353
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970350774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3970350774
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3366298933
Short name	T28
Test name
Test status
Simulation time	205200107 ps
CPU time	2.19 seconds
Started	Jul 01 10:44:05 AM PDT 24
Finished	Jul 01 10:44:08 AM PDT 24
Peak memory	204432 kb
Host	smart-956e3374-c6c1-429f-a352-fb457c6f2797
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366298933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3366298933
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1080378475
Short name	T24
Test name
Test status
Simulation time	76690455 ps
CPU time	3.14 seconds
Started	Jul 01 10:44:36 AM PDT 24
Finished	Jul 01 10:44:41 AM PDT 24
Peak memory	204484 kb
Host	smart-3af446ff-d534-4859-8c7b-363cd5efcc2c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080378475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1080378475
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2177098543
Short name	T62
Test name
Test status
Simulation time	59146368 ps
CPU time	0.99 seconds
Started	Jul 01 10:44:15 AM PDT 24
Finished	Jul 01 10:44:16 AM PDT 24
Peak memory	204540 kb
Host	smart-add6643a-d1a1-4aa3-b401-4eb9b4d6066e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177098543 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2177098543
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3218453804
Short name	T138
Test name
Test status
Simulation time	16366549 ps
CPU time	0.78 seconds
Started	Jul 01 10:44:20 AM PDT 24
Finished	Jul 01 10:44:22 AM PDT 24
Peak memory	204508 kb
Host	smart-c05273a5-93b4-4291-8e89-e34d876a3e2d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218453804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3218453804
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2042932372
Short name	T16
Test name
Test status
Simulation time	23939215 ps
CPU time	0.92 seconds
Started	Jul 01 10:44:21 AM PDT 24
Finished	Jul 01 10:44:23 AM PDT 24
Peak memory	204416 kb
Host	smart-ae744289-9d98-4f2e-b682-cfab74f096f3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042932372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.2042932372
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1413821500
Short name	T106
Test name
Test status
Simulation time	66488964 ps
CPU time	1.78 seconds
Started	Jul 01 10:44:08 AM PDT 24
Finished	Jul 01 10:44:11 AM PDT 24
Peak memory	204580 kb
Host	smart-dc837ec9-6202-40ef-8caf-2808743232ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413821500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1413821500
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.795193555
Short name	T59
Test name
Test status
Simulation time	285310250 ps
CPU time	2.14 seconds
Started	Jul 01 10:44:28 AM PDT 24
Finished	Jul 01 10:44:30 AM PDT 24
Peak memory	204340 kb
Host	smart-075cb490-9970-4f64-8207-b3c30097dddc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795193555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.795193555
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.1369210548
Short name	T75
Test name
Test status
Simulation time	20735939 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:25 AM PDT 24
Finished	Jul 01 10:44:27 AM PDT 24
Peak memory	204312 kb
Host	smart-93385bab-2007-47a6-aa7c-85e675078825
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369210548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1369210548
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1678066274
Short name	T54
Test name
Test status
Simulation time	19554226 ps
CPU time	0.71 seconds
Started	Jul 01 10:44:42 AM PDT 24
Finished	Jul 01 10:44:43 AM PDT 24
Peak memory	204328 kb
Host	smart-4c4dbede-9ac0-41c5-b21a-3dfba5534586
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678066274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1678066274
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.3704194756
Short name	T99
Test name
Test status
Simulation time	20266848 ps
CPU time	0.73 seconds
Started	Jul 01 10:44:48 AM PDT 24
Finished	Jul 01 10:44:49 AM PDT 24
Peak memory	204556 kb
Host	smart-d2608050-4ea8-4bf7-8753-31b0a818c7ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704194756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3704194756
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3629066899
Short name	T78
Test name
Test status
Simulation time	44032914 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:53 AM PDT 24
Finished	Jul 01 10:44:54 AM PDT 24
Peak memory	204312 kb
Host	smart-a78f8925-e9a1-4b38-b750-ac776d4ee6dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629066899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3629066899
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2905210851
Short name	T155
Test name
Test status
Simulation time	27911995 ps
CPU time	0.64 seconds
Started	Jul 01 10:44:46 AM PDT 24
Finished	Jul 01 10:44:47 AM PDT 24
Peak memory	204336 kb
Host	smart-85fb8532-47d6-495c-aaa2-8f646cd90c13
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905210851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2905210851
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2045337015
Short name	T157
Test name
Test status
Simulation time	33460228 ps
CPU time	0.63 seconds
Started	Jul 01 10:44:46 AM PDT 24
Finished	Jul 01 10:44:48 AM PDT 24
Peak memory	204256 kb
Host	smart-d64bac65-ec68-4dbf-927b-83e4b667eb15
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045337015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2045337015
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.559746037
Short name	T110
Test name
Test status
Simulation time	28646579 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:47 AM PDT 24
Finished	Jul 01 10:44:48 AM PDT 24
Peak memory	204336 kb
Host	smart-69b87467-aa97-444c-87c2-b590043ffbe8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559746037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.559746037
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.393713558
Short name	T135
Test name
Test status
Simulation time	34790998 ps
CPU time	0.67 seconds
Started	Jul 01 10:44:24 AM PDT 24
Finished	Jul 01 10:44:25 AM PDT 24
Peak memory	204308 kb
Host	smart-cff7e71d-acac-4a6a-a2d8-906294ad95a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393713558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.393713558
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.3632758250
Short name	T151
Test name
Test status
Simulation time	65279930 ps
CPU time	0.66 seconds
Started	Jul 01 10:44:24 AM PDT 24
Finished	Jul 01 10:44:30 AM PDT 24
Peak memory	204312 kb
Host	smart-52936a6e-3c8e-461c-9343-2765a83fc003
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632758250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3632758250
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.754437831
Short name	T53
Test name
Test status
Simulation time	16124836 ps
CPU time	0.69 seconds
Started	Jul 01 10:44:26 AM PDT 24
Finished	Jul 01 10:44:28 AM PDT 24
Peak memory	204296 kb
Host	smart-6a073152-e5d0-48f5-8831-530ea2de0b19
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754437831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.754437831
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.385531226
Short name	T4
Test name
Test status
Simulation time	34746974 ps
CPU time	0.92 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204440 kb
Host	smart-4b39bdc7-a750-4807-93be-e10a843dd749
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385531226 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.385531226
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3243818891
Short name	T121
Test name
Test status
Simulation time	30323567 ps
CPU time	0.83 seconds
Started	Jul 01 10:44:17 AM PDT 24
Finished	Jul 01 10:44:19 AM PDT 24
Peak memory	204364 kb
Host	smart-8d08f748-798e-4ac1-ac9f-2e64f831dc54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243818891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3243818891
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.3153134186
Short name	T81
Test name
Test status
Simulation time	49434720 ps
CPU time	0.7 seconds
Started	Jul 01 10:44:34 AM PDT 24
Finished	Jul 01 10:44:36 AM PDT 24
Peak memory	204328 kb
Host	smart-d82afa40-7dbc-4ccc-a79e-447c75d0389c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153134186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3153134186
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1024051541
Short name	T97
Test name
Test status
Simulation time	49715890 ps
CPU time	1.09 seconds
Started	Jul 01 10:44:50 AM PDT 24
Finished	Jul 01 10:44:56 AM PDT 24
Peak memory	204548 kb
Host	smart-a78f8118-8100-41a9-a52a-49259b2da2a2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024051541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.1024051541
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1382573355
Short name	T115
Test name
Test status
Simulation time	110895923 ps
CPU time	2.41 seconds
Started	Jul 01 10:44:37 AM PDT 24
Finished	Jul 01 10:44:40 AM PDT 24
Peak memory	204528 kb
Host	smart-5363dece-4db9-442f-b493-61db83a48486
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382573355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1382573355
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4236699394
Short name	T20
Test name
Test status
Simulation time	22918527 ps
CPU time	0.87 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:13 AM PDT 24
Peak memory	204428 kb
Host	smart-e68338e3-0f94-40b0-948d-450f52a2b1ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236699394 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4236699394
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.3281362800
Short name	T34
Test name
Test status
Simulation time	75563995 ps
CPU time	0.82 seconds
Started	Jul 01 10:44:39 AM PDT 24
Finished	Jul 01 10:44:40 AM PDT 24
Peak memory	204384 kb
Host	smart-afbac05d-ec50-4573-ab20-8f247cab1add
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281362800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3281362800
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.226269427
Short name	T120
Test name
Test status
Simulation time	26743402 ps
CPU time	0.69 seconds
Started	Jul 01 10:44:11 AM PDT 24
Finished	Jul 01 10:44:12 AM PDT 24
Peak memory	204332 kb
Host	smart-85daea1f-2f81-46ae-bd31-6d8b0bceda00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226269427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.226269427
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.61904248
Short name	T126
Test name
Test status
Simulation time	35138814 ps
CPU time	0.98 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204400 kb
Host	smart-2351f8c8-4f47-4a17-882f-f7d4ee7a1b8f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61904248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outs tanding.61904248
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2086777419
Short name	T23
Test name
Test status
Simulation time	81549626 ps
CPU time	1.91 seconds
Started	Jul 01 10:44:19 AM PDT 24
Finished	Jul 01 10:44:21 AM PDT 24
Peak memory	204572 kb
Host	smart-ff1f6bea-c081-4772-990a-c2f76a25f856
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086777419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2086777419
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1789183863
Short name	T102
Test name
Test status
Simulation time	28565019 ps
CPU time	1.27 seconds
Started	Jul 01 10:44:33 AM PDT 24
Finished	Jul 01 10:44:35 AM PDT 24
Peak memory	212752 kb
Host	smart-ebfb4f4f-b270-42ee-8091-074713926049
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789183863 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1789183863
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3415013538
Short name	T125
Test name
Test status
Simulation time	19199643 ps
CPU time	0.75 seconds
Started	Jul 01 10:44:08 AM PDT 24
Finished	Jul 01 10:44:10 AM PDT 24
Peak memory	204624 kb
Host	smart-ca44b335-3f9f-4ec1-90c0-d0e8bb7e8cab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415013538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3415013538
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.3845219491
Short name	T154
Test name
Test status
Simulation time	37147637 ps
CPU time	0.64 seconds
Started	Jul 01 10:44:23 AM PDT 24
Finished	Jul 01 10:44:24 AM PDT 24
Peak memory	204236 kb
Host	smart-ebb9c240-90a1-4354-8e81-a9191c8b3292
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845219491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3845219491
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4067778357
Short name	T45
Test name
Test status
Simulation time	158716919 ps
CPU time	1.12 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:14 AM PDT 24
Peak memory	204456 kb
Host	smart-269913de-1480-425e-add6-cfc879d4dcea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067778357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.4067778357
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.840489999
Short name	T89
Test name
Test status
Simulation time	76823199 ps
CPU time	2.14 seconds
Started	Jul 01 10:44:36 AM PDT 24
Finished	Jul 01 10:44:40 AM PDT 24
Peak memory	204544 kb
Host	smart-58225108-293e-4d46-94ab-d842ff33b4e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840489999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.840489999
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1871637236
Short name	T64
Test name
Test status
Simulation time	133670959 ps
CPU time	2.4 seconds
Started	Jul 01 10:44:22 AM PDT 24
Finished	Jul 01 10:44:25 AM PDT 24
Peak memory	204372 kb
Host	smart-b9ab47e1-f138-4fc0-a150-0dcc40f82fc7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871637236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1871637236
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.66328800
Short name	T109
Test name
Test status
Simulation time	24847733 ps
CPU time	0.82 seconds
Started	Jul 01 10:44:12 AM PDT 24
Finished	Jul 01 10:44:13 AM PDT 24
Peak memory	204428 kb
Host	smart-fc1d6265-e92c-4130-b6f5-02836a76b3c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66328800 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.66328800
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.923710123
Short name	T84
Test name
Test status
Simulation time	43133441 ps
CPU time	0.78 seconds
Started	Jul 01 10:44:07 AM PDT 24
Finished	Jul 01 10:44:09 AM PDT 24
Peak memory	204400 kb
Host	smart-bad54b86-3f60-4a25-87ec-28639461aae2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923710123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.923710123
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.2975736667
Short name	T15
Test name
Test status
Simulation time	38318124 ps
CPU time	0.64 seconds
Started	Jul 01 10:44:09 AM PDT 24
Finished	Jul 01 10:44:11 AM PDT 24
Peak memory	204316 kb
Host	smart-2d39bc82-744d-4c66-b110-48b5a39952e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975736667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2975736667
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.637583586
Short name	T149
Test name
Test status
Simulation time	49874562 ps
CPU time	2.53 seconds
Started	Jul 01 10:44:09 AM PDT 24
Finished	Jul 01 10:44:12 AM PDT 24
Peak memory	212764 kb
Host	smart-634f6a54-7086-4c2b-86b4-3d0a67b47f14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637583586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.637583586
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.74761295
Short name	T56
Test name
Test status
Simulation time	84651059 ps
CPU time	1.42 seconds
Started	Jul 01 10:44:31 AM PDT 24
Finished	Jul 01 10:44:33 AM PDT 24
Peak memory	204416 kb
Host	smart-0792e8b1-e1ce-44d9-b91b-fa4d8aaf7dbe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74761295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.74761295
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2024573926
Short name	T26
Test name
Test status
Simulation time	154265776 ps
CPU time	1.1 seconds
Started	Jul 01 10:44:13 AM PDT 24
Finished	Jul 01 10:44:15 AM PDT 24
Peak memory	204464 kb
Host	smart-d0d497c6-466a-4fed-ad53-22d1a3131373
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024573926 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2024573926
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.2957697669
Short name	T40
Test name
Test status
Simulation time	44504862 ps
CPU time	0.72 seconds
Started	Jul 01 10:44:49 AM PDT 24
Finished	Jul 01 10:44:50 AM PDT 24
Peak memory	204508 kb
Host	smart-2a488abb-20a7-43be-b1ac-d19820eb6990
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957697669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2957697669
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.118479873
Short name	T10
Test name
Test status
Simulation time	43032098 ps
CPU time	0.71 seconds
Started	Jul 01 10:44:09 AM PDT 24
Finished	Jul 01 10:44:11 AM PDT 24
Peak memory	204260 kb
Host	smart-00f67909-3774-45a7-8e3a-98dbe8144ae8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118479873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.118479873
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3245194061
Short name	T124
Test name
Test status
Simulation time	53083897 ps
CPU time	1.3 seconds
Started	Jul 01 10:44:36 AM PDT 24
Finished	Jul 01 10:44:39 AM PDT 24
Peak memory	204540 kb
Host	smart-1571b8bd-688c-44bc-9f9b-66ca2d8791d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245194061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3245194061
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.148553858
Short name	T66
Test name
Test status
Simulation time	162542282 ps
CPU time	2.22 seconds
Started	Jul 01 10:44:48 AM PDT 24
Finished	Jul 01 10:44:50 AM PDT 24
Peak memory	204496 kb
Host	smart-7eb0d000-adbc-496e-9e35-bd910513b6b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148553858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.148553858
Directory	/workspace/9.i2c_tl_intg_err/latest