Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	326	1			T6	1		T18	1		T9	8
all_pins[1]	326	1			T6	1		T18	1		T9	8
all_pins[2]	326	1			T6	1		T18	1		T9	8
all_pins[3]	326	1			T6	1		T18	1		T9	8
all_pins[4]	326	1			T6	1		T18	1		T9	8
all_pins[5]	326	1			T6	1		T18	1		T9	8
all_pins[6]	326	1			T6	1		T18	1		T9	8
all_pins[7]	326	1			T6	1		T18	1		T9	8
all_pins[8]	326	1			T6	1		T18	1		T9	8
all_pins[9]	326	1			T6	1		T18	1		T9	8
all_pins[10]	326	1			T6	1		T18	1		T9	8
all_pins[11]	326	1			T6	1		T18	1		T9	8
all_pins[12]	326	1			T6	1		T18	1		T9	8
all_pins[13]	326	1			T6	1		T18	1		T9	8
all_pins[14]	326	1			T6	1		T18	1		T9	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4081	1			T6	15		T18	15		T9	102
values[0x1]	809	1			T9	18		T10	16		T11	29
transitions[0x0=>0x1]	623	1			T9	15		T10	11		T11	22
transitions[0x1=>0x0]	632	1			T9	15		T10	11		T11	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285	1			T6	1		T18	1		T9	7
all_pins[0]	values[0x1]	41	1			T9	1		T10	2		T11	1
all_pins[0]	transitions[0x0=>0x1]	33	1			T9	1		T10	1		T11	1
all_pins[0]	transitions[0x1=>0x0]	34	1			T10	1		T11	1		T15	1
all_pins[1]	values[0x0]	284	1			T6	1		T18	1		T9	8
all_pins[1]	values[0x1]	42	1			T10	2		T11	1		T15	1
all_pins[1]	transitions[0x0=>0x1]	30	1			T10	2		T11	1		T15	1
all_pins[1]	transitions[0x1=>0x0]	49	1			T9	2		T10	1		T11	2
all_pins[2]	values[0x0]	265	1			T6	1		T18	1		T9	6
all_pins[2]	values[0x1]	61	1			T9	2		T10	1		T11	2
all_pins[2]	transitions[0x0=>0x1]	48	1			T9	2		T10	1		T11	2
all_pins[2]	transitions[0x1=>0x0]	53	1			T11	4		T12	1		T13	4
all_pins[3]	values[0x0]	260	1			T6	1		T18	1		T9	8
all_pins[3]	values[0x1]	66	1			T11	4		T12	1		T13	4
all_pins[3]	transitions[0x0=>0x1]	55	1			T11	3		T12	1		T13	4
all_pins[3]	transitions[0x1=>0x0]	29	1			T9	1		T11	1		T12	1
all_pins[4]	values[0x0]	286	1			T6	1		T18	1		T9	7
all_pins[4]	values[0x1]	40	1			T9	1		T11	2		T12	1
all_pins[4]	transitions[0x0=>0x1]	27	1			T11	1		T12	1		T72	1
all_pins[4]	transitions[0x1=>0x0]	44	1			T9	1		T10	2		T11	1
all_pins[5]	values[0x0]	269	1			T6	1		T18	1		T9	6
all_pins[5]	values[0x1]	57	1			T9	2		T10	2		T11	2
all_pins[5]	transitions[0x0=>0x1]	48	1			T9	1		T10	2		T11	1
all_pins[5]	transitions[0x1=>0x0]	54	1			T11	2		T15	2		T12	2
all_pins[6]	values[0x0]	263	1			T6	1		T18	1		T9	7
all_pins[6]	values[0x1]	63	1			T9	1		T11	3		T15	2
all_pins[6]	transitions[0x0=>0x1]	51	1			T9	1		T11	2		T15	1
all_pins[6]	transitions[0x1=>0x0]	52	1			T9	1		T10	3		T11	2
all_pins[7]	values[0x0]	262	1			T6	1		T18	1		T9	7
all_pins[7]	values[0x1]	64	1			T9	1		T10	3		T11	3
all_pins[7]	transitions[0x0=>0x1]	47	1			T9	1		T10	2		T11	3
all_pins[7]	transitions[0x1=>0x0]	38	1			T11	1		T72	3		T73	2
all_pins[8]	values[0x0]	271	1			T6	1		T18	1		T9	8
all_pins[8]	values[0x1]	55	1			T10	1		T11	1		T13	1
all_pins[8]	transitions[0x0=>0x1]	41	1			T11	1		T13	1		T72	2
all_pins[8]	transitions[0x1=>0x0]	44	1			T11	1		T72	2		T74	3
all_pins[9]	values[0x0]	268	1			T6	1		T18	1		T9	8
all_pins[9]	values[0x1]	58	1			T10	1		T11	1		T72	3
all_pins[9]	transitions[0x0=>0x1]	52	1			T72	3		T75	1		T74	3
all_pins[9]	transitions[0x1=>0x0]	46	1			T9	2		T11	1		T12	1
all_pins[10]	values[0x0]	274	1			T6	1		T18	1		T9	6
all_pins[10]	values[0x1]	52	1			T9	2		T10	1		T11	2
all_pins[10]	transitions[0x0=>0x1]	38	1			T9	2		T10	1		T11	1
all_pins[10]	transitions[0x1=>0x0]	40	1			T9	3		T10	1		T11	2
all_pins[11]	values[0x0]	272	1			T6	1		T18	1		T9	5
all_pins[11]	values[0x1]	54	1			T9	3		T10	1		T11	3
all_pins[11]	transitions[0x0=>0x1]	39	1			T9	3		T11	3		T13	1
all_pins[11]	transitions[0x1=>0x0]	36	1			T9	1		T10	1		T12	2
all_pins[12]	values[0x0]	275	1			T6	1		T18	1		T9	7
all_pins[12]	values[0x1]	51	1			T9	1		T10	2		T15	1
all_pins[12]	transitions[0x0=>0x1]	39	1			T10	2		T15	1		T12	2
all_pins[12]	transitions[0x1=>0x0]	41	1			T9	2		T11	2		T15	1
all_pins[13]	values[0x0]	273	1			T6	1		T18	1		T9	5
all_pins[13]	values[0x1]	53	1			T9	3		T11	2		T15	1
all_pins[13]	transitions[0x0=>0x1]	39	1			T9	3		T11	1		T15	1
all_pins[13]	transitions[0x1=>0x0]	38	1			T9	1		T11	1		T12	1
all_pins[14]	values[0x0]	274	1			T6	1		T18	1		T9	7
all_pins[14]	values[0x1]	52	1			T9	1		T11	2		T12	1
all_pins[14]	transitions[0x0=>0x1]	36	1			T9	1		T11	2		T12	1
all_pins[14]	transitions[0x1=>0x0]	34	1			T9	1		T10	2		T11	1