SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.interrupts_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 45 | 0 | 45 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acq_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 368 | 1 | T1 | 4 | T11 | 10 | T8 | 10 | ||||
auto[1] | 240 | 1 | T1 | 10 | T11 | 8 | T8 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 111 | 1 | T1 | 4 | T11 | 2 | T8 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 395 | 1 | T1 | 14 | T11 | 10 | T8 | 16 | ||||
auto[1] | 238 | 1 | T1 | 5 | T8 | 5 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 112 | 1 | T1 | 1 | T11 | 1 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 353 | 1 | T11 | 11 | T8 | 10 | T12 | 4 | ||||
auto[1] | 269 | 1 | T1 | 5 | T11 | 1 | T8 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 129 | 1 | T1 | 3 | T11 | 1 | T8 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 388 | 1 | T1 | 5 | T11 | 12 | T8 | 9 | ||||
auto[1] | 328 | 1 | T1 | 4 | T11 | 2 | T8 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 115 | 1 | T1 | 2 | T11 | 1 | T8 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 374 | 1 | T1 | 1 | T11 | 1 | T8 | 1 | ||||
auto[1] | 365 | 1 | T1 | 8 | T11 | 7 | T8 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 121 | 1 | T1 | 4 | T11 | 2 | T8 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 300 | 1 | T1 | 12 | T8 | 12 | T10 | 4 | ||||
auto[1] | 348 | 1 | T1 | 5 | T8 | 5 | T10 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 128 | 1 | T1 | 3 | T11 | 1 | T8 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 380 | 1 | T1 | 13 | T11 | 6 | T8 | 6 | ||||
auto[1] | 296 | 1 | T11 | 12 | T8 | 11 | T9 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 109 | 1 | T1 | 3 | T11 | 1 | T8 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 372 | 1 | T1 | 12 | T8 | 1 | T10 | 13 | ||||
auto[1] | 318 | 1 | T1 | 5 | T8 | 4 | T9 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 129 | 1 | T1 | 3 | T11 | 1 | T8 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 312 | 1 | T1 | 1 | T8 | 3 | T10 | 8 | ||||
auto[1] | 329 | 1 | T1 | 16 | T8 | 14 | T10 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 136 | 1 | T1 | 6 | T8 | 5 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 406 | 1 | T1 | 1 | T11 | 18 | T8 | 1 | ||||
auto[1] | 237 | 1 | T1 | 4 | T8 | 9 | T12 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 114 | 1 | T1 | 4 | T8 | 3 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 350 | 1 | T1 | 2 | T8 | 16 | T10 | 6 | ||||
auto[1] | 341 | 1 | T1 | 22 | T11 | 4 | T10 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 131 | 1 | T1 | 4 | T11 | 2 | T10 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 430 | 1 | T1 | 1 | T11 | 2 | T8 | 11 | ||||
auto[1] | 353 | 1 | T1 | 16 | T11 | 16 | T8 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 119 | 1 | T1 | 3 | T11 | 2 | T8 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 358 | 1 | T1 | 3 | T11 | 12 | T8 | 9 | ||||
auto[1] | 250 | 1 | T1 | 5 | T8 | 2 | T10 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 116 | 1 | T1 | 3 | T8 | 3 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 363 | 1 | T1 | 7 | T8 | 8 | T10 | 4 | ||||
auto[1] | 305 | 1 | T1 | 8 | T11 | 4 | T8 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 110 | 1 | T1 | 2 | T11 | 2 | T8 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 304 | 1 | T1 | 2 | T11 | 8 | T8 | 2 | ||||
auto[1] | 289 | 1 | T1 | 21 | T8 | 15 | T10 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 121 | 1 | T1 | 3 | T8 | 5 | T10 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |