Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

43905

1

T1

18

T2

52

T3

298

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38496	1			T1	20		T2	73		T3	423
values[0x0]	16916	1			T1	5		T2	29		T3	136
values[0x1]	17536	1			T1	15		T2	31		T3	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20389	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52559

1

T1

24

T2

69

T3

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	291	1			T3	12		T7	1		T6	1
valid_sources[0x01]	385	1			T7	2		T13	3		T4	1
valid_sources[0x02]	329	1			T3	6		T7	1		T6	1
valid_sources[0x03]	309	1			T7	5		T6	7		T4	16
valid_sources[0x04]	373	1			T2	1		T7	1		T6	10
valid_sources[0x05]	331	1			T3	4		T7	2		T6	2
valid_sources[0x06]	337	1			T6	6		T13	2		T4	2
valid_sources[0x07]	295	1			T7	1		T13	1		T14	5
valid_sources[0x08]	188	1			T6	1		T4	14		T21	19
valid_sources[0x09]	340	1			T2	1		T7	5		T6	6
valid_sources[0x0a]	385	1			T7	3		T6	1		T13	1
valid_sources[0x0b]	439	1			T3	1		T6	1		T13	3
valid_sources[0x0c]	246	1			T3	4		T7	3		T6	3
valid_sources[0x0d]	236	1			T3	3		T7	2		T4	4
valid_sources[0x0e]	403	1			T7	2		T6	3		T13	1
valid_sources[0x0f]	289	1			T3	3		T6	1		T13	1
valid_sources[0x10]	263	1			T7	3		T13	3		T4	3
valid_sources[0x11]	243	1			T2	3		T3	1		T7	9
valid_sources[0x12]	487	1			T3	6		T7	5		T6	5
valid_sources[0x13]	261	1			T7	2		T6	3		T13	4
valid_sources[0x14]	274	1			T7	4		T13	4		T4	2
valid_sources[0x15]	221	1			T3	8		T7	3		T6	1
valid_sources[0x16]	259	1			T3	18		T7	4		T13	1
valid_sources[0x17]	248	1			T2	1		T13	1		T4	10
valid_sources[0x18]	364	1			T2	1		T3	2		T7	2
valid_sources[0x19]	353	1			T3	1		T7	2		T6	3
valid_sources[0x1a]	208	1			T7	2		T6	1		T13	1
valid_sources[0x1b]	237	1			T3	7		T7	2		T6	2
valid_sources[0x1c]	173	1			T2	3		T7	4		T6	2
valid_sources[0x1d]	208	1			T7	2		T6	2		T4	11
valid_sources[0x1e]	187	1			T3	2		T13	2		T4	1
valid_sources[0x1f]	214	1			T3	2		T7	3		T6	1
valid_sources[0x20]	245	1			T3	2		T7	3		T6	1
valid_sources[0x21]	245	1			T2	2		T3	1		T6	10
valid_sources[0x22]	218	1			T2	1		T3	7		T7	1
valid_sources[0x23]	257	1			T2	1		T6	2		T13	1
valid_sources[0x24]	294	1			T2	1		T7	4		T4	4
valid_sources[0x25]	170	1			T7	3		T6	1		T13	5
valid_sources[0x26]	300	1			T3	3		T7	1		T6	1
valid_sources[0x27]	319	1			T7	1		T6	1		T4	7
valid_sources[0x28]	295	1			T7	1		T6	1		T13	1
valid_sources[0x29]	497	1			T3	9		T7	4		T6	1
valid_sources[0x2a]	274	1			T3	8		T7	2		T6	1
valid_sources[0x2b]	286	1			T3	3		T7	1		T6	8
valid_sources[0x2c]	338	1			T3	9		T7	1		T6	1
valid_sources[0x2d]	417	1			T3	1		T7	1		T6	3
valid_sources[0x2e]	253	1			T3	2		T7	1		T6	10
valid_sources[0x2f]	219	1			T7	2		T4	12		T21	25
valid_sources[0x30]	207	1			T7	5		T6	2		T21	23
valid_sources[0x31]	305	1			T7	2		T6	6		T13	4
valid_sources[0x32]	316	1			T3	1		T7	5		T6	1
valid_sources[0x33]	297	1			T7	3		T6	6		T21	58
valid_sources[0x34]	283	1			T7	1		T6	3		T13	2
valid_sources[0x35]	258	1			T2	2		T7	6		T6	1
valid_sources[0x36]	217	1			T2	1		T3	2		T7	4
valid_sources[0x37]	312	1			T3	2		T7	1		T6	1
valid_sources[0x38]	227	1			T7	6		T6	5		T13	4
valid_sources[0x39]	389	1			T2	1		T3	7		T6	1
valid_sources[0x3a]	276	1			T2	2		T3	4		T7	1
valid_sources[0x3b]	286	1			T7	5		T13	1		T4	4
valid_sources[0x3c]	288	1			T7	1		T6	10		T4	7
valid_sources[0x3d]	233	1			T3	7		T7	2		T21	4
valid_sources[0x3e]	252	1			T3	5		T7	3		T13	2
valid_sources[0x3f]	245	1			T3	11		T7	4		T6	3
valid_sources[0x40]	265	1			T7	4		T6	3		T13	1
valid_sources[0x41]	257	1			T3	1		T7	4		T13	2
valid_sources[0x42]	241	1			T7	1		T6	6		T4	3
valid_sources[0x43]	227	1			T7	5		T6	2		T13	1
valid_sources[0x44]	320	1			T3	8		T7	5		T13	2
valid_sources[0x45]	282	1			T2	1		T7	2		T6	2
valid_sources[0x46]	302	1			T3	4		T7	2		T6	12
valid_sources[0x47]	266	1			T3	4		T7	1		T6	2
valid_sources[0x48]	343	1			T3	3		T7	2		T6	1
valid_sources[0x49]	265	1			T7	1		T13	2		T4	10
valid_sources[0x4a]	258	1			T2	2		T7	3		T6	4
valid_sources[0x4b]	288	1			T3	6		T7	2		T6	3
valid_sources[0x4c]	294	1			T7	1		T6	9		T4	6
valid_sources[0x4d]	451	1			T7	2		T13	2		T8	3
valid_sources[0x4e]	257	1			T7	5		T4	2		T21	27
valid_sources[0x4f]	358	1			T7	2		T6	9		T4	6
valid_sources[0x50]	311	1			T3	2		T7	2		T6	3
valid_sources[0x51]	215	1			T3	1		T7	2		T21	27
valid_sources[0x52]	267	1			T2	2		T3	5		T7	1
valid_sources[0x53]	297	1			T2	1		T3	2		T7	2
valid_sources[0x54]	302	1			T7	1		T6	1		T4	7
valid_sources[0x55]	263	1			T2	1		T7	4		T6	3
valid_sources[0x56]	220	1			T7	3		T6	6		T4	13
valid_sources[0x57]	249	1			T7	4		T6	2		T13	2
valid_sources[0x58]	372	1			T2	2		T3	8		T7	4
valid_sources[0x59]	247	1			T3	3		T7	3		T6	7
valid_sources[0x5a]	281	1			T3	4		T6	1		T4	17
valid_sources[0x5b]	356	1			T3	6		T7	4		T6	3
valid_sources[0x5c]	225	1			T3	3		T7	4		T6	2
valid_sources[0x5d]	297	1			T2	3		T7	3		T13	1
valid_sources[0x5e]	378	1			T3	6		T7	1		T6	1
valid_sources[0x5f]	275	1			T2	1		T7	3		T6	5
valid_sources[0x60]	270	1			T3	2		T7	1		T13	3
valid_sources[0x61]	320	1			T7	3		T13	2		T4	14
valid_sources[0x62]	229	1			T2	1		T7	6		T4	3
valid_sources[0x63]	273	1			T3	5		T7	1		T13	1
valid_sources[0x64]	233	1			T7	4		T6	3		T13	1
valid_sources[0x65]	265	1			T2	5		T3	10		T7	2
valid_sources[0x66]	230	1			T3	6		T7	2		T6	1
valid_sources[0x67]	256	1			T3	9		T7	3		T4	10
valid_sources[0x68]	354	1			T13	1		T4	9		T14	14
valid_sources[0x69]	330	1			T7	3		T6	3		T13	3
valid_sources[0x6a]	308	1			T7	2		T13	2		T4	2
valid_sources[0x6b]	241	1			T3	1		T7	4		T6	1
valid_sources[0x6c]	350	1			T2	1		T7	2		T6	3
valid_sources[0x6d]	199	1			T3	1		T7	3		T13	4
valid_sources[0x6e]	254	1			T7	5		T6	1		T13	2
valid_sources[0x6f]	372	1			T2	8		T7	2		T6	2
valid_sources[0x70]	265	1			T7	2		T6	4		T8	3
valid_sources[0x71]	313	1			T7	4		T6	4		T11	22
valid_sources[0x72]	218	1			T7	3		T6	1		T4	4
valid_sources[0x73]	276	1			T3	8		T7	4		T13	1
valid_sources[0x74]	303	1			T3	6		T7	1		T6	6
valid_sources[0x75]	274	1			T3	11		T7	4		T6	3
valid_sources[0x76]	257	1			T3	13		T7	1		T13	4
valid_sources[0x77]	248	1			T2	1		T3	4		T7	3
valid_sources[0x78]	304	1			T7	2		T6	7		T13	4
valid_sources[0x79]	250	1			T2	1		T3	1		T7	5
valid_sources[0x7a]	329	1			T3	5		T7	3		T13	3
valid_sources[0x7b]	327	1			T7	2		T6	2		T4	2
valid_sources[0x7c]	288	1			T7	5		T6	5		T13	1
valid_sources[0x7d]	264	1			T2	2		T3	3		T7	5
valid_sources[0x7e]	242	1			T7	4		T13	4		T4	7
valid_sources[0x7f]	265	1			T2	2		T7	4		T6	1
valid_sources[0x80]	189	1			T7	3		T6	10		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16493

1

T1

12

T2

14

T3

77

values[0x0]

all_enables

biggest_size

14182

1

T1

2

T2

17

T3

107

values[0x1]

all_enables

biggest_size

13230

1

T1

4

T2

21

T3

114