Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	771899	0	0	0
ctrl_rd_A	771899	2996	0	0
host_fifo_config_rd_A	771899	2043	0	0
host_nack_handler_timeout_rd_A	771899	2178	0	0
host_timeout_ctrl_rd_A	771899	1830	0	0
intr_enable_rd_A	771899	4796	0	0
ovrd_rd_A	771899	2029	0	0
target_fifo_config_rd_A	771899	1948	0	0
target_id_rd_A	771899	2346	0	0
target_timeout_ctrl_rd_A	771899	2119	0	0
timeout_ctrl_rd_A	771899	2008	0	0
timing0_rd_A	771899	2028	0	0
timing1_rd_A	771899	2023	0	0
timing2_rd_A	771899	2028	0	0
timing3_rd_A	771899	2191	0	0
timing4_rd_A	771899	2048	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2996	0	0
T2	1665	12	0	0
T3	7590	124	0	0
T4	7357	0	0	0
T5	0	214	0	0
T6	9648	0	0	0
T7	6909	70	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	44	0	0
T15	0	76	0	0
T17	0	352	0	0
T18	0	33	0	0
T24	0	183	0	0
T50	0	4	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2043	0	0
T2	1665	5	0	0
T3	7590	37	0	0
T4	7357	0	0	0
T5	0	72	0	0
T6	9648	0	0	0
T7	6909	24	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	34	0	0
T15	0	15	0	0
T17	0	101	0	0
T18	0	5	0	0
T24	0	55	0	0
T50	0	46	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2178	0	0
T2	1665	2	0	0
T3	7590	52	0	0
T4	7357	0	0	0
T5	0	134	0	0
T6	9648	0	0	0
T7	6909	83	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	50	0	0
T15	0	21	0	0
T17	0	93	0	0
T18	0	11	0	0
T24	0	55	0	0
T50	0	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	1830	0	0
T2	1665	8	0	0
T3	7590	29	0	0
T4	7357	0	0	0
T5	0	84	0	0
T6	9648	0	0	0
T7	6909	78	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	54	0	0
T15	0	16	0	0
T17	0	81	0	0
T18	0	1	0	0
T24	0	37	0	0
T50	0	46	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	4796	0	0
T2	1665	3	0	0
T3	7590	309	0	0
T4	7357	0	0	0
T5	0	704	0	0
T6	9648	0	0	0
T7	6909	60	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	25	0	0
T15	0	75	0	0
T17	0	681	0	0
T18	0	39	0	0
T50	0	39	0	0
T52	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2029	0	0
T2	1665	7	0	0
T3	7590	54	0	0
T4	7357	0	0	0
T5	0	153	0	0
T6	9648	0	0	0
T7	6909	30	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	23	0	0
T15	0	11	0	0
T17	0	146	0	0
T18	0	11	0	0
T24	0	84	0	0
T50	0	16	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	1948	0	0
T2	1665	3	0	0
T3	7590	55	0	0
T4	7357	0	0	0
T5	0	110	0	0
T6	9648	0	0	0
T7	6909	28	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	27	0	0
T15	0	27	0	0
T17	0	90	0	0
T18	0	6	0	0
T24	0	34	0	0
T50	0	29	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2346	0	0
T2	1665	10	0	0
T3	7590	71	0	0
T4	7357	0	0	0
T5	0	221	0	0
T6	9648	0	0	0
T7	6909	17	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	36	0	0
T15	0	46	0	0
T17	0	173	0	0
T18	0	14	0	0
T24	0	76	0	0
T50	0	38	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2119	0	0
T2	1665	10	0	0
T3	7590	54	0	0
T4	7357	0	0	0
T5	0	117	0	0
T6	9648	0	0	0
T7	6909	61	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	37	0	0
T15	0	34	0	0
T17	0	117	0	0
T18	0	11	0	0
T24	0	46	0	0
T50	0	20	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2008	0	0
T3	7590	64	0	0
T4	7357	0	0	0
T5	0	124	0	0
T6	9648	0	0	0
T7	6909	48	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	26	0	0
T15	0	19	0	0
T17	0	178	0	0
T18	0	16	0	0
T21	12748	0	0	0
T24	0	60	0	0
T38	0	21	0	0
T50	0	22	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2028	0	0
T2	1665	12	0	0
T3	7590	48	0	0
T4	7357	0	0	0
T5	0	184	0	0
T6	9648	0	0	0
T7	6909	48	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	25	0	0
T15	0	20	0	0
T17	0	85	0	0
T18	0	10	0	0
T24	0	40	0	0
T50	0	28	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2023	0	0
T2	1665	3	0	0
T3	7590	48	0	0
T4	7357	0	0	0
T5	0	113	0	0
T6	9648	0	0	0
T7	6909	47	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	34	0	0
T15	0	35	0	0
T17	0	92	0	0
T18	0	8	0	0
T24	0	58	0	0
T50	0	50	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2028	0	0
T2	1665	4	0	0
T3	7590	47	0	0
T4	7357	0	0	0
T5	0	107	0	0
T6	9648	0	0	0
T7	6909	34	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	45	0	0
T15	0	31	0	0
T17	0	125	0	0
T18	0	20	0	0
T24	0	58	0	0
T50	0	11	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2191	0	0
T2	1665	7	0	0
T3	7590	53	0	0
T4	7357	0	0	0
T5	0	124	0	0
T6	9648	0	0	0
T7	6909	56	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	41	0	0
T15	0	17	0	0
T17	0	145	0	0
T18	0	2	0	0
T24	0	50	0	0
T50	0	42	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771899	2048	0	0
T3	7590	61	0	0
T4	7357	0	0	0
T5	0	107	0	0
T6	9648	0	0	0
T7	6909	76	0	0
T8	1976	0	0	0
T10	1050	0	0	0
T11	1038	0	0	0
T13	1999	0	0	0
T14	14703	26	0	0
T15	0	20	0	0
T17	0	129	0	0
T18	0	11	0	0
T21	12748	0	0	0
T24	0	55	0	0
T38	0	30	0	0
T50	0	30	0	0