Unified Coverage Report :: Module :: prim_ram_1p_adv

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_ram_1p	0.00	0.00				0.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_ram_1p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00
u_req_d_buf	0.00	0.00
u_write_d_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		23	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	3	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	138	0	0
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	248	0	0
CONT_ASSIGN	249	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	311	1	0	0.00
CONT_ASSIGN	312	1	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	314	0	0
CONT_ASSIGN	353	1	0	0.00
CONT_ASSIGN	354	1	0	0.00
CONT_ASSIGN	356	0	0
CONT_ASSIGN	359	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	0	1
103	0	1
123	0	1
126	0	1
127	0	1
129	0	1
133	0	1
134	0	1
135	0	1
136	0	1
137	0	1
138		unreachable
147	0	1
156	0	1
248		unreachable
249	0	1
251	0	1
255	0	1
310	0	1
311	0	1
312	0	1
313	0	1
314		unreachable
353	0	1
354	0	1
356		unreachable
359	0	1

---

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	126	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	126	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered