Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

184331

1

T6

1024

T30

256

T41

337

ack

15396

1

T2

20

T6

32

T30

2

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	734	1			T6	5		T41	2		T74	7
high	41243	1			T2	4		T6	214		T30	58
med	74565	1			T2	3		T6	390		T30	111
sml	82389	1			T2	13		T6	437		T30	88
all_zero	796	1			T6	10		T30	1		T41	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99526

1

T2

10

T6

512

T30

135

auto[1]

100201

1

T2

10

T6

544

T30

123

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136838

1

T2

20

T6

691

T30

175

auto[1]

62889

1

T6

365

T30

83

T41

118

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

191684

1

T2

10

T6

1041

T30

258

auto[1]

8043

1

T2

10

T6

15

T41

4

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

188867

1

T2

10

T6

1025

T30

256

auto[1]

10860

1

T2

10

T6

31

T30

2

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189856

1

T2

10

T6

1026

T30

257

auto[1]

9871

1

T2

10

T6

30

T30

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99526

1

T2

10

T6

512

T30

135

auto[1]

100201

1

T2

10

T6

544

T30

123

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136838

1

T2

20

T6

691

T30

175

auto[1]

62889

1

T6

365

T30

83

T41

118

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

191684

1

T2

10

T6

1041

T30

258

auto[1]

8043

1

T2

10

T6

15

T41

4

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

188867

1

T2

10

T6

1025

T30

256

auto[1]

10860

1

T2

10

T6

31

T30

2

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189856

1

T2

10

T6

1026

T30

257

auto[1]

9871

1

T2

10

T6

30

T30

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T264

1

T265

1

T266

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T267

1

T54

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T268

1

T269

1

T270

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

349

1

T6

2

T74

1

T75

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

186

1

T6

2

T51

1

T75

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

185

1

T6

2

T51

2

T74

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

593

1

T6

3

T41

1

T51

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

306

1

T6

1

T41

1

T51

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

300

1

T6

2

T75

2

T40

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

633

1

T6

6

T41

2

T51

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

320

1

T6

3

T51

2

T74

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

291

1

T51

1

T74

3

T75

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T271

1

T272

1

T273

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T274

1

T54

1

T275

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T6

1

T57

1

T276

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	58468	1			T6	296		T30	85		T41	105
write_address_byte	10860	1			T2	10		T6	31		T30	2
read_with_ack	2188	1			T59	15		T173	9		T40	1
read_with_nack	5855	1			T2	10		T6	15		T41	4
stop_byte	9871	1			T2	10		T6	30		T30	1
write_address_byte_nak	5716	1			T6	28		T41	5		T51	24
data_byte_nack	184331	1			T6	1024		T30	256		T41	337
stop_byte_nack	6136	1			T6	27		T30	1		T41	3
nakok_byte_nack	92442	1			T6	525		T30	122		T41	179
nakok_addr_byte_nack	2909	1			T6	17		T41	3		T51	12