Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48428921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11126865

1

T1

26

T2

60621

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58785827	1			T1	24		T2	122281		T3	51
values[0x0]	384805	1			T1	13		T2	118		T3	11
values[0x1]	385154	1			T1	19		T2	101		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34619913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24935873

1

T1

29

T2

73408

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	212577	1			T2	477		T6	6		T7	49
valid_sources[0x01]	207062	1			T1	4		T2	415		T3	1
valid_sources[0x02]	202213	1			T2	487		T6	4		T8	3
valid_sources[0x03]	224419	1			T2	473		T3	2		T6	3
valid_sources[0x04]	259039	1			T2	482		T6	4		T8	7
valid_sources[0x05]	195117	1			T2	472		T5	1		T6	3
valid_sources[0x06]	223558	1			T2	487		T6	5		T8	13
valid_sources[0x07]	217978	1			T1	1		T2	474		T6	7
valid_sources[0x08]	215668	1			T2	494		T6	6		T8	12
valid_sources[0x09]	214963	1			T2	527		T6	5		T8	7
valid_sources[0x0a]	213019	1			T2	461		T5	1		T6	991
valid_sources[0x0b]	231210	1			T2	438		T6	911		T8	3
valid_sources[0x0c]	209815	1			T2	494		T3	3		T6	4841
valid_sources[0x0d]	223172	1			T2	451		T6	6		T8	4
valid_sources[0x0e]	233986	1			T2	491		T6	8		T8	3
valid_sources[0x0f]	219061	1			T2	481		T6	3		T8	4
valid_sources[0x10]	238581	1			T2	504		T3	1		T6	4
valid_sources[0x11]	205171	1			T2	488		T6	8		T8	2
valid_sources[0x12]	241856	1			T2	494		T6	2781		T8	4
valid_sources[0x13]	198169	1			T2	471		T6	4		T8	10
valid_sources[0x14]	319974	1			T2	516		T6	3		T7	91
valid_sources[0x15]	200803	1			T2	471		T6	4		T7	43
valid_sources[0x16]	232073	1			T2	491		T6	2287		T8	11
valid_sources[0x17]	207061	1			T2	489		T6	5		T7	1
valid_sources[0x18]	217545	1			T2	507		T6	4		T8	9
valid_sources[0x19]	211464	1			T2	499		T6	4		T7	4
valid_sources[0x1a]	204345	1			T1	1		T2	482		T6	4
valid_sources[0x1b]	205457	1			T2	487		T5	1		T6	3
valid_sources[0x1c]	240028	1			T2	494		T6	2		T8	6
valid_sources[0x1d]	217049	1			T2	512		T6	1		T30	1
valid_sources[0x1e]	203352	1			T2	444		T6	4		T7	3
valid_sources[0x1f]	207390	1			T2	471		T6	1		T8	5
valid_sources[0x20]	234246	1			T2	462		T6	4		T8	6
valid_sources[0x21]	203085	1			T2	512		T5	2		T6	5
valid_sources[0x22]	206771	1			T2	512		T6	5		T7	23
valid_sources[0x23]	200659	1			T2	438		T6	6		T8	4
valid_sources[0x24]	207761	1			T2	467		T6	7		T8	4
valid_sources[0x25]	211156	1			T2	453		T6	9		T8	20
valid_sources[0x26]	212104	1			T2	481		T6	3		T8	13
valid_sources[0x27]	230583	1			T2	439		T6	6951		T7	3
valid_sources[0x28]	220395	1			T2	433		T6	5		T8	3
valid_sources[0x29]	225960	1			T2	464		T6	7		T8	1
valid_sources[0x2a]	202200	1			T2	499		T6	4		T7	28
valid_sources[0x2b]	212584	1			T2	460		T6	5		T8	3
valid_sources[0x2c]	239256	1			T2	507		T6	2126		T7	46
valid_sources[0x2d]	203337	1			T2	496		T6	5		T7	5
valid_sources[0x2e]	289528	1			T2	501		T6	6		T8	11
valid_sources[0x2f]	201575	1			T2	459		T6	2		T7	6
valid_sources[0x30]	217171	1			T2	533		T6	7		T8	5
valid_sources[0x31]	231174	1			T2	444		T5	2		T6	2
valid_sources[0x32]	213950	1			T2	471		T6	9		T8	3
valid_sources[0x33]	202290	1			T2	435		T6	3		T8	9
valid_sources[0x34]	236041	1			T2	458		T6	8		T7	25
valid_sources[0x35]	219692	1			T2	435		T6	7		T8	8
valid_sources[0x36]	205702	1			T2	435		T6	9		T7	58
valid_sources[0x37]	201107	1			T2	478		T6	3		T8	9
valid_sources[0x38]	225709	1			T2	464		T5	1		T6	2
valid_sources[0x39]	207508	1			T2	510		T6	7501		T8	7
valid_sources[0x3a]	206506	1			T1	5		T2	449		T5	2
valid_sources[0x3b]	232855	1			T1	2		T2	475		T6	6
valid_sources[0x3c]	200368	1			T2	462		T6	2		T7	1
valid_sources[0x3d]	240277	1			T2	492		T6	8		T8	19
valid_sources[0x3e]	337516	1			T2	458		T6	2		T7	20
valid_sources[0x3f]	211896	1			T2	454		T6	4		T8	8
valid_sources[0x40]	206337	1			T2	452		T6	4		T8	10
valid_sources[0x41]	219185	1			T2	490		T6	4310		T8	8
valid_sources[0x42]	202196	1			T2	489		T6	7		T7	1
valid_sources[0x43]	223239	1			T2	483		T5	1		T6	719
valid_sources[0x44]	219932	1			T2	438		T6	4		T9	1
valid_sources[0x45]	205919	1			T2	473		T6	7		T8	4
valid_sources[0x46]	236557	1			T2	510		T6	195		T8	3
valid_sources[0x47]	645868	1			T2	499		T6	3233		T8	9
valid_sources[0x48]	234886	1			T2	435		T5	1		T6	4068
valid_sources[0x49]	218329	1			T2	426		T6	6		T7	1
valid_sources[0x4a]	210019	1			T2	523		T6	2		T8	4
valid_sources[0x4b]	207751	1			T2	545		T6	3		T8	9
valid_sources[0x4c]	208817	1			T2	469		T6	8		T8	2
valid_sources[0x4d]	206671	1			T2	483		T6	3		T8	1
valid_sources[0x4e]	220414	1			T1	1		T2	485		T5	1
valid_sources[0x4f]	217451	1			T2	462		T6	4175		T8	5
valid_sources[0x50]	204569	1			T2	475		T6	2		T8	6
valid_sources[0x51]	210810	1			T2	485		T6	7347		T8	7
valid_sources[0x52]	205917	1			T2	529		T6	3		T8	4
valid_sources[0x53]	204977	1			T2	481		T6	6		T7	57
valid_sources[0x54]	219965	1			T2	486		T6	4		T8	5
valid_sources[0x55]	227543	1			T2	462		T3	2		T6	6848
valid_sources[0x56]	384297	1			T2	478		T6	193		T8	2
valid_sources[0x57]	213712	1			T2	481		T6	4		T7	11
valid_sources[0x58]	224321	1			T2	477		T6	2		T8	5
valid_sources[0x59]	207580	1			T2	489		T6	5		T8	1
valid_sources[0x5a]	220820	1			T2	511		T5	1		T6	5
valid_sources[0x5b]	223517	1			T2	513		T5	2		T6	2
valid_sources[0x5c]	218847	1			T2	511		T6	6		T8	8
valid_sources[0x5d]	223241	1			T2	475		T6	2		T7	42
valid_sources[0x5e]	236597	1			T2	487		T6	8		T7	14
valid_sources[0x5f]	214560	1			T1	3		T2	476		T6	3
valid_sources[0x60]	236382	1			T2	483		T3	2		T6	4
valid_sources[0x61]	200105	1			T1	1		T2	472		T6	3
valid_sources[0x62]	207301	1			T1	1		T2	476		T3	2
valid_sources[0x63]	225655	1			T2	465		T6	1		T8	2
valid_sources[0x64]	222645	1			T2	485		T6	2		T7	38
valid_sources[0x65]	211989	1			T2	450		T6	3		T8	8
valid_sources[0x66]	195800	1			T2	487		T6	4		T7	15
valid_sources[0x67]	216671	1			T2	485		T6	4		T8	8
valid_sources[0x68]	209020	1			T2	481		T6	4		T8	7
valid_sources[0x69]	213943	1			T2	478		T3	3		T6	5
valid_sources[0x6a]	223586	1			T2	484		T6	193		T7	10
valid_sources[0x6b]	220542	1			T2	506		T6	3		T8	7
valid_sources[0x6c]	235011	1			T2	491		T3	2		T5	2
valid_sources[0x6d]	231698	1			T2	499		T6	7		T7	31
valid_sources[0x6e]	206003	1			T2	462		T6	1552		T7	11
valid_sources[0x6f]	416590	1			T2	466		T6	3		T8	7
valid_sources[0x70]	204037	1			T2	460		T6	4		T8	3
valid_sources[0x71]	203302	1			T2	507		T6	6		T10	1
valid_sources[0x72]	270393	1			T2	504		T6	4		T8	5
valid_sources[0x73]	256022	1			T2	469		T6	5		T7	13
valid_sources[0x74]	210443	1			T2	474		T6	6		T8	3
valid_sources[0x75]	209248	1			T2	449		T3	3		T6	6
valid_sources[0x76]	234366	1			T2	456		T6	3		T8	14
valid_sources[0x77]	193195	1			T2	444		T6	6		T8	3
valid_sources[0x78]	996012	1			T2	432		T6	5		T8	12
valid_sources[0x79]	226447	1			T2	458		T6	9		T7	4
valid_sources[0x7a]	223269	1			T2	475		T3	1		T6	1296
valid_sources[0x7b]	219834	1			T1	6		T2	493		T3	3
valid_sources[0x7c]	228221	1			T1	2		T2	479		T6	6465
valid_sources[0x7d]	223721	1			T2	475		T6	5		T8	3
valid_sources[0x7e]	204549	1			T2	467		T3	1		T6	6
valid_sources[0x7f]	565690	1			T2	478		T6	6		T10	2
valid_sources[0x80]	234484	1			T2	463		T5	1		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10750973

1

T1

10

T2

60442

T3

20

values[0x0]

all_enables

biggest_size

217011

1

T1

11

T2

99

T3

8

values[0x1]

all_enables

biggest_size

158881

1

T1

5

T2

80

T3

4