Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_target_cg	87.50	1	100	1	64	64
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	1	7	87.50	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for B2B_txn_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write_after_read_same_addr	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	46	1			T92	2		T239	1		T283	1
b2b_read_same_addr	281	1			T7	1		T24	1		T25	1
write_after_read_different_addr	39	1			T7	1		T21	1		T284	1
read_after_write_different_addr	40	1			T11	1		T27	1		T20	1
read_after_write_same_addr	1	1			T285	1		-	-		-	-
b2b_write_different_addr	49	1			T1	1		T14	1		T103	1
b2b_write_same_addr	248	1			T14	1		T11	2		T15	1

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3585	1			T2	3		T6	9		T41	3
b2b_read_same_addr	270	1			T40	1		T156	2		T52	1
write_after_read_different_addr	3644	1			T2	4		T6	7		T41	1
write_after_read_same_addr	68	1			T74	1		T286	1		T43	1
read_after_write_different_addr	3644	1			T2	3		T6	6		T41	1
read_after_write_same_addr	45	1			T271	1		T287	1		T288	1
b2b_write_different_addr	3533	1			T2	9		T6	9		T30	1
b2b_write_same_addr	259	1			T41	3		T42	1		T36	1