Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	391041128	0	0	0
ctrl_rd_A	391041128	2917	0	0
host_fifo_config_rd_A	391041128	5681	0	0
host_nack_handler_timeout_rd_A	391041128	2000	0	0
host_timeout_ctrl_rd_A	391041128	1911	0	0
intr_enable_rd_A	391041128	4736	0	0
ovrd_rd_A	391041128	2898	0	0
target_fifo_config_rd_A	391041128	1879	0	0
target_id_rd_A	391041128	2412	0	0
target_timeout_ctrl_rd_A	391041128	1970	0	0
timeout_ctrl_rd_A	391041128	2116	0	0
timing0_rd_A	391041128	2053	0	0
timing1_rd_A	391041128	2011	0	0
timing2_rd_A	391041128	2021	0	0
timing3_rd_A	391041128	2036	0	0
timing4_rd_A	391041128	2105	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2917	0	0
T104	2952	3	0	0
T105	5367	53	0	0
T106	2592	5	0	0
T107	5355	29	0	0
T108	3152	21	0	0
T109	5773	125	0	0
T110	2094	57	0	0
T111	8812	22	0	0
T112	5785	14	0	0
T113	3342	36	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	5681	0	0
T22	81098	0	0	0
T38	194848	120	0	0
T114	532258	137	0	0
T115	0	220	0	0
T116	0	219	0	0
T117	0	90	0	0
T118	0	183	0	0
T119	0	259	0	0
T120	0	146	0	0
T121	0	317	0	0
T122	0	187	0	0
T123	4894	0	0	0
T124	11328	0	0	0
T125	26178	0	0	0
T126	140324	0	0	0
T127	119463	0	0	0
T128	31800	0	0	0
T129	34222	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2000	0	0
T104	2952	6	0	0
T105	5367	60	0	0
T106	2592	4	0	0
T107	5355	7	0	0
T108	3152	24	0	0
T109	5773	132	0	0
T110	2094	11	0	0
T111	8812	23	0	0
T112	5785	14	0	0
T130	3775	15	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	1911	0	0
T104	2952	17	0	0
T105	5367	53	0	0
T106	2592	11	0	0
T107	5355	27	0	0
T108	3152	27	0	0
T109	5773	114	0	0
T110	2094	7	0	0
T111	8812	21	0	0
T112	5785	38	0	0
T130	3775	41	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	4736	0	0
T104	0	4	0	0
T105	0	46	0	0
T116	128122	12	0	0
T118	0	13	0	0
T130	0	34	0	0
T131	0	23	0	0
T132	0	21	0	0
T133	0	56	0	0
T134	0	4	0	0
T135	0	24	0	0
T136	12557	0	0	0
T137	257520	0	0	0
T138	6599	0	0	0
T139	175074	0	0	0
T140	53021	0	0	0
T141	28349	0	0	0
T142	225281	0	0	0
T143	16332	0	0	0
T144	132199	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2898	0	0
T9	1920	34	0	0
T10	771271	0	0	0
T11	17709	0	0	0
T14	15431	0	0	0
T15	12882	0	0	0
T16	637643	0	0	0
T30	168962	0	0	0
T31	9810	0	0	0
T32	53194	0	0	0
T41	156321	0	0	0
T99	0	53	0	0
T145	0	36	0	0
T146	0	39	0	0
T147	0	58	0	0
T148	0	43	0	0
T149	0	40	0	0
T150	0	40	0	0
T151	0	37	0	0
T152	0	55	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	1879	0	0
T104	2952	12	0	0
T105	5367	68	0	0
T106	2592	6	0	0
T107	5355	24	0	0
T108	3152	34	0	0
T109	5773	115	0	0
T110	2094	9	0	0
T111	8812	16	0	0
T112	5785	13	0	0
T130	3775	6	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2412	0	0
T104	2952	21	0	0
T105	5367	59	0	0
T106	2592	10	0	0
T107	5355	11	0	0
T108	3152	17	0	0
T109	5773	133	0	0
T110	2094	9	0	0
T111	8812	16	0	0
T113	3342	18	0	0
T153	5721	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	1970	0	0
T104	2952	28	0	0
T105	5367	53	0	0
T106	2592	7	0	0
T107	5355	19	0	0
T108	3152	7	0	0
T109	5773	108	0	0
T110	2094	11	0	0
T111	8812	3	0	0
T112	5785	3	0	0
T130	3775	9	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2116	0	0
T104	2952	11	0	0
T105	5367	71	0	0
T106	2592	13	0	0
T107	5355	12	0	0
T108	3152	24	0	0
T109	5773	105	0	0
T110	2094	17	0	0
T111	8812	12	0	0
T112	5785	24	0	0
T130	3775	12	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2053	0	0
T105	5367	70	0	0
T106	2592	8	0	0
T107	5355	12	0	0
T108	3152	16	0	0
T109	5773	146	0	0
T110	2094	10	0	0
T111	8812	30	0	0
T112	5785	7	0	0
T130	3775	3	0	0
T153	5721	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2011	0	0
T104	2952	2	0	0
T105	5367	86	0	0
T106	2592	8	0	0
T107	5355	30	0	0
T108	3152	42	0	0
T109	5773	126	0	0
T110	2094	11	0	0
T111	8812	18	0	0
T112	5785	18	0	0
T130	3775	1	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2021	0	0
T104	2952	14	0	0
T105	5367	61	0	0
T106	2592	14	0	0
T107	5355	38	0	0
T108	3152	25	0	0
T109	5773	108	0	0
T110	2094	13	0	0
T111	8812	23	0	0
T112	5785	42	0	0
T130	3775	20	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2036	0	0
T104	2952	11	0	0
T105	5367	85	0	0
T106	2592	8	0	0
T107	5355	31	0	0
T108	3152	35	0	0
T109	5773	97	0	0
T111	8812	30	0	0
T112	5785	33	0	0
T113	3342	21	0	0
T130	3775	11	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391041128	2105	0	0
T104	2952	24	0	0
T105	5367	72	0	0
T106	2592	15	0	0
T107	5355	26	0	0
T108	3152	16	0	0
T109	5773	133	0	0
T110	2094	6	0	0
T111	8812	13	0	0
T112	5785	38	0	0
T130	3775	19	0	0