Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

174248

1

T2

640

T4

35

T7

2

ack

15194

1

T2

20

T4

4

T7

5

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	704	1			T2	1		T4	1		T8	1
high	38860	1			T2	129		T4	5		T7	1
med	70527	1			T2	254		T4	15		T7	3
sml	78639	1			T2	272		T4	18		T7	2
all_zero	712	1			T2	4		T7	1		T41	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94718

1

T2

326

T4

17

T7

5

auto[1]

94724

1

T2

334

T4

22

T7

2

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129913

1

T2

447

T4

28

T7

6

auto[1]

59529

1

T2

213

T4

11

T7

1

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181560

1

T2

651

T4

38

T7

5

auto[1]

7882

1

T2

9

T4

1

T7

2

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178883

1

T2

641

T4

36

T7

3

auto[1]

10559

1

T2

19

T4

3

T7

4

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179917

1

T2

642

T4

38

T7

4

auto[1]

9525

1

T2

18

T4

1

T7

3

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94718

1

T2

326

T4

17

T7

5

auto[1]

94724

1

T2

334

T4

22

T7

2

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129913

1

T2

447

T4

28

T7

6

auto[1]

59529

1

T2

213

T4

11

T7

1

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181560

1

T2

651

T4

38

T7

5

auto[1]

7882

1

T2

9

T4

1

T7

2

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178883

1

T2

641

T4

36

T7

3

auto[1]

10559

1

T2

19

T4

3

T7

4

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179917

1

T2

642

T4

38

T7

4

auto[1]

9525

1

T2

18

T4

1

T7

3

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T274

1

T275

1

T276

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T108

1

T277

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T278

1

T279

1

T54

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

289

1

T4

1

T42

1

T46

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

172

1

T75

1

T46

1

T180

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

147

1

T251

1

T42

1

T46

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

574

1

T2

2

T4

1

T251

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

296

1

T75

1

T42

1

T46

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

296

1

T278

1

T102

4

T280

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

587

1

T2

4

T42

3

T102

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

272

1

T75

1

T251

1

T42

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

282

1

T2

2

T42

1

T278

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T281

1

T51

1

T282

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T49

1

T81

1

T283

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T284

1

T285

1

T57

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	55412	1			T2	211		T4	11		T33	2
write_address_byte	10559	1			T2	19		T4	3		T7	4
read_with_ack	2207	1			T8	7		T33	4		T34	17
read_with_nack	5675	1			T2	9		T4	1		T7	2
stop_byte	9525	1			T2	18		T4	1		T7	3
write_address_byte_nak	5374	1			T2	16		T4	2		T33	5
data_byte_nack	174248	1			T2	640		T4	35		T7	2
stop_byte_nack	5824	1			T2	15		T7	2		T33	4
nakok_byte_nack	87168	1			T2	321		T4	18		T33	10
nakok_addr_byte_nack	2689	1			T2	7		T4	1		T33	3