Unified Coverage Report :: Group :: i2c_env_pkg::i2c_status_cg

Group : i2c_env_pkg::i2c_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.status_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group Instance i2c_env_pkg.status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acqempty	2	0	2	100.00	100	1	1	2
cp_acqfull	2	0	2	100.00	100	1	1	2
cp_fmtempty	2	0	2	100.00	100	1	1	2
cp_fmtfull	2	0	2	100.00	100	1	1	2
cp_hostidle	2	0	2	100.00	100	1	1	2
cp_rxempty	2	0	2	100.00	100	1	1	2
cp_rxfull	2	0	2	100.00	100	1	1	2
cp_targetidle	2	0	2	100.00	100	1	1	2
cp_txempty	2	0	2	100.00	100	1	1	2
cp_txfull	2	0	2	100.00	100	1	1	2

Summary for Variable cp_acqempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1730642

1

T6

374

T11

4

T12

18683

auto[1]

41613329

1

T1

170

T2

36993

T3

5880

---

Summary for Variable cp_acqfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43328324

1

T1

170

T2

36993

T3

5880

auto[1]

15647

1

T18

98

T19

521

T20

566

---

Summary for Variable cp_fmtempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40131819

1

T1

110

T2

35488

T3

5877

auto[1]

3212152

1

T1

60

T2

1505

T3

3

---

Summary for Variable cp_fmtfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37197831

1

T1

170

T2

36993

T3

5880

auto[1]

6146140

1

T158

17999

T159

8721

T75

3488

---

Summary for Variable cp_hostidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_hostidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40127764

1

T1

110

T2

35488

T3

5877

auto[1]

3216207

1

T1

60

T2

1505

T3

3

---

Summary for Variable cp_rxempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11099388

1

T2

18495

T3

5671

T4

679

auto[1]

32244583

1

T1

170

T2

18498

T3

209

---

Summary for Variable cp_rxfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43254566

1

T1

170

T2

36950

T3

5880

auto[1]

89405

1

T2

43

T74

1

T58

569

---

Summary for Variable cp_targetidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_targetidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2742085

1

T6

428

T11

8

T12

18718

auto[1]

40601886

1

T1

170

T2

36993

T3

5880

---

Summary for Variable cp_txempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2678580

1

T11

5

T12

18710

T16

48

auto[1]

40665391

1

T1

170

T2

36993

T3

5880

---

Summary for Variable cp_txfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42963619

1

T1

170

T2

36993

T3

5880

auto[1]

380352

1

T27

3710

T90

3960

T91

6009