Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 36490311 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 10618098 1 T1 84 T2 9209 T3 2963



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 46393689 1 T1 178 T2 37684 T3 5883
values[0x0] 356477 1 T1 50 T2 375 T3 10
values[0x1] 358243 1 T1 56 T2 451 T3 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 25700109 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 21408300 1 T1 153 T2 17748 T3 3546



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 183062 1 T1 1 T2 129 T4 1461
valid_sources[0x01] 172597 1 T2 102 T4 1366 T7 140
valid_sources[0x02] 166778 1 T2 208 T4 1481 T7 171
valid_sources[0x03] 180782 1 T2 134 T4 1362 T7 152
valid_sources[0x04] 183608 1 T2 168 T4 1332 T7 187
valid_sources[0x05] 174842 1 T1 3 T2 171 T4 1425
valid_sources[0x06] 185024 1 T1 1 T2 125 T4 1374
valid_sources[0x07] 175126 1 T2 136 T4 1432 T7 172
valid_sources[0x08] 172983 1 T2 133 T4 1414 T5 2
valid_sources[0x09] 182029 1 T1 1 T2 101 T4 1433
valid_sources[0x0a] 172229 1 T1 1 T2 109 T4 1338
valid_sources[0x0b] 163690 1 T2 131 T4 1338 T7 190
valid_sources[0x0c] 175167 1 T2 114 T4 1312 T7 156
valid_sources[0x0d] 168961 1 T1 1 T2 129 T4 1325
valid_sources[0x0e] 169606 1 T1 1 T2 159 T4 1317
valid_sources[0x0f] 177610 1 T2 181 T4 1326 T7 172
valid_sources[0x10] 196592 1 T2 136 T4 1360 T7 175
valid_sources[0x11] 187392 1 T2 176 T4 1420 T7 193
valid_sources[0x12] 174126 1 T2 180 T4 1402 T7 176
valid_sources[0x13] 174708 1 T1 3 T2 129 T4 1432
valid_sources[0x14] 169757 1 T1 2 T2 127 T3 24
valid_sources[0x15] 170918 1 T1 1 T2 178 T4 1409
valid_sources[0x16] 165014 1 T2 149 T4 1305 T7 171
valid_sources[0x17] 217187 1 T1 1 T2 143 T4 1396
valid_sources[0x18] 170945 1 T2 130 T4 1425 T7 157
valid_sources[0x19] 166378 1 T1 1 T2 109 T4 1425
valid_sources[0x1a] 174382 1 T1 1 T2 128 T4 1323
valid_sources[0x1b] 163923 1 T1 1 T2 124 T4 1449
valid_sources[0x1c] 194142 1 T1 2 T2 155 T4 1465
valid_sources[0x1d] 182665 1 T2 168 T4 1300 T7 173
valid_sources[0x1e] 167015 1 T2 188 T4 1388 T7 179
valid_sources[0x1f] 165004 1 T1 2 T2 167 T4 1355
valid_sources[0x20] 180651 1 T1 1 T2 161 T4 1420
valid_sources[0x21] 176554 1 T1 1 T2 111 T4 1297
valid_sources[0x22] 175373 1 T2 181 T4 1327 T7 159
valid_sources[0x23] 173190 1 T1 1 T2 138 T4 1431
valid_sources[0x24] 283737 1 T1 1 T2 182 T4 1346
valid_sources[0x25] 171216 1 T2 164 T4 1370 T7 187
valid_sources[0x26] 188629 1 T1 2 T2 151 T4 1385
valid_sources[0x27] 188614 1 T2 132 T4 1350 T7 160
valid_sources[0x28] 177868 1 T1 1 T2 161 T4 1460
valid_sources[0x29] 199056 1 T1 2 T2 149 T4 1339
valid_sources[0x2a] 195135 1 T1 2 T2 127 T4 1379
valid_sources[0x2b] 175198 1 T2 213 T4 1372 T7 170
valid_sources[0x2c] 213105 1 T1 2 T2 161 T4 1265
valid_sources[0x2d] 172588 1 T2 118 T4 1317 T5 1
valid_sources[0x2e] 185946 1 T1 2 T2 131 T4 1349
valid_sources[0x2f] 188427 1 T2 137 T4 1344 T7 185
valid_sources[0x30] 171652 1 T2 166 T4 1438 T7 200
valid_sources[0x31] 181669 1 T2 151 T4 1273 T7 193
valid_sources[0x32] 167812 1 T1 1 T2 159 T4 1463
valid_sources[0x33] 197566 1 T2 123 T4 1409 T7 182
valid_sources[0x34] 178888 1 T1 3 T2 165 T4 1299
valid_sources[0x35] 174984 1 T1 2 T2 131 T4 1401
valid_sources[0x36] 170471 1 T1 1 T2 162 T4 1413
valid_sources[0x37] 171226 1 T2 130 T4 1320 T7 152
valid_sources[0x38] 193712 1 T1 2 T2 147 T4 1390
valid_sources[0x39] 181728 1 T1 3 T2 177 T4 1427
valid_sources[0x3a] 163676 1 T1 2 T2 168 T4 1378
valid_sources[0x3b] 290369 1 T1 3 T2 127 T4 1395
valid_sources[0x3c] 204009 1 T1 1 T2 119 T4 1406
valid_sources[0x3d] 178377 1 T1 1 T2 190 T4 1395
valid_sources[0x3e] 190785 1 T1 2 T2 173 T4 1403
valid_sources[0x3f] 174967 1 T1 4 T2 134 T4 1403
valid_sources[0x40] 176330 1 T2 129 T4 1402 T7 175
valid_sources[0x41] 180076 1 T2 148 T4 1406 T7 179
valid_sources[0x42] 192030 1 T1 2 T2 157 T4 1429
valid_sources[0x43] 166687 1 T1 2 T2 89 T4 1390
valid_sources[0x44] 176059 1 T2 183 T4 1415 T7 169
valid_sources[0x45] 171221 1 T1 1 T2 129 T4 1498
valid_sources[0x46] 168939 1 T1 1 T2 120 T4 1426
valid_sources[0x47] 180268 1 T2 191 T4 1386 T7 160
valid_sources[0x48] 180587 1 T2 119 T4 1381 T6 76
valid_sources[0x49] 172415 1 T2 126 T4 1311 T7 168
valid_sources[0x4a] 172002 1 T2 149 T4 1344 T7 184
valid_sources[0x4b] 174178 1 T1 1 T2 146 T4 1385
valid_sources[0x4c] 186972 1 T2 113 T4 1381 T5 2
valid_sources[0x4d] 175808 1 T1 3 T2 207 T4 1409
valid_sources[0x4e] 170557 1 T1 1 T2 148 T4 1346
valid_sources[0x4f] 191242 1 T1 1 T2 150 T4 1354
valid_sources[0x50] 190002 1 T1 1 T2 140 T4 1349
valid_sources[0x51] 178693 1 T1 2 T2 144 T4 1426
valid_sources[0x52] 182032 1 T2 186 T4 1434 T7 171
valid_sources[0x53] 169387 1 T1 3 T2 182 T4 1347
valid_sources[0x54] 184019 1 T2 164 T4 1414 T5 2
valid_sources[0x55] 174195 1 T1 1 T2 184 T4 1462
valid_sources[0x56] 186214 1 T1 1 T2 147 T4 1374
valid_sources[0x57] 177794 1 T1 2 T2 133 T4 1384
valid_sources[0x58] 164861 1 T1 1 T2 202 T4 1406
valid_sources[0x59] 179663 1 T1 2 T2 140 T4 1466
valid_sources[0x5a] 168553 1 T1 3 T2 169 T4 1506
valid_sources[0x5b] 175752 1 T2 152 T4 1437 T7 164
valid_sources[0x5c] 180141 1 T1 3 T2 159 T4 1456
valid_sources[0x5d] 209818 1 T1 2 T2 161 T4 1331
valid_sources[0x5e] 170061 1 T2 129 T4 1359 T7 167
valid_sources[0x5f] 189765 1 T1 1 T2 139 T4 1340
valid_sources[0x60] 193253 1 T1 1 T2 121 T4 1465
valid_sources[0x61] 253681 1 T1 2 T2 140 T4 1433
valid_sources[0x62] 164324 1 T2 199 T4 1401 T7 166
valid_sources[0x63] 171018 1 T1 3 T2 137 T4 1394
valid_sources[0x64] 185456 1 T2 155 T4 1390 T7 190
valid_sources[0x65] 192302 1 T1 4 T2 150 T4 1330
valid_sources[0x66] 181110 1 T1 1 T2 138 T4 1329
valid_sources[0x67] 159108 1 T1 2 T2 160 T4 1279
valid_sources[0x68] 168282 1 T1 1 T2 161 T4 1364
valid_sources[0x69] 172480 1 T2 119 T4 1269 T7 192
valid_sources[0x6a] 173369 1 T2 114 T4 1402 T7 158
valid_sources[0x6b] 167444 1 T1 1 T2 179 T4 1409
valid_sources[0x6c] 167117 1 T1 2 T2 198 T4 1402
valid_sources[0x6d] 164811 1 T1 1 T2 115 T4 1378
valid_sources[0x6e] 165175 1 T1 1 T2 91 T4 1414
valid_sources[0x6f] 163793 1 T2 160 T4 1403 T7 148
valid_sources[0x70] 159921 1 T2 115 T4 1397 T7 174
valid_sources[0x71] 170786 1 T1 1 T2 165 T4 1401
valid_sources[0x72] 184667 1 T1 2 T2 125 T4 1347
valid_sources[0x73] 192499 1 T1 2 T2 174 T4 1321
valid_sources[0x74] 349500 1 T1 2 T2 113 T4 1466
valid_sources[0x75] 161577 1 T2 177 T4 1384 T7 175
valid_sources[0x76] 208468 1 T1 2 T2 156 T4 1448
valid_sources[0x77] 320806 1 T2 152 T4 1374 T7 186
valid_sources[0x78] 201297 1 T1 1 T2 143 T4 1376
valid_sources[0x79] 170837 1 T2 141 T4 1403 T7 156
valid_sources[0x7a] 171409 1 T1 1 T2 140 T4 1382
valid_sources[0x7b] 174324 1 T1 2 T2 159 T4 1473
valid_sources[0x7c] 164549 1 T2 161 T4 1320 T7 169
valid_sources[0x7d] 165780 1 T2 132 T4 1370 T7 146
valid_sources[0x7e] 168349 1 T1 1 T2 159 T4 1398
valid_sources[0x7f] 174401 1 T2 136 T4 1417 T7 139
valid_sources[0x80] 180242 1 T2 117 T4 1350 T7 166



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 10264398 1 T1 14 T2 8782 T3 2953
values[0x0] all_enables biggest_size 202788 1 T1 37 T2 235 T3 6
values[0x1] all_enables biggest_size 150912 1 T1 33 T2 192 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%