Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_target_cg	87.50	1	100	1	64	64
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	1	7	87.50	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for B2B_txn_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_after_write_same_addr	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	37	1			T11	2		T292	1		T112	1
b2b_read_same_addr	253	1			T11	5		T27	1		T23	1
write_after_read_different_addr	50	1			T24	1		T85	1		T293	1
write_after_read_same_addr	1	1			T294	1		-	-		-	-
read_after_write_different_addr	42	1			T91	1		T295	1		T296	2
b2b_write_different_addr	54	1			T155	1		T297	1		T298	1
b2b_write_same_addr	296	1			T12	1		T16	1		T17	1

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3573	1			T2	4		T8	12		T33	3
b2b_read_same_addr	261	1			T33	2		T75	2		T42	7
write_after_read_different_addr	3510	1			T2	5		T7	1		T8	9
write_after_read_same_addr	62	1			T34	1		T36	1		T39	1
read_after_write_different_addr	3509	1			T2	5		T7	1		T8	9
read_after_write_same_addr	51	1			T39	1		T40	1		T64	2
b2b_write_different_addr	3568	1			T2	5		T4	1		T7	1
b2b_write_same_addr	295	1			T4	2		T7	1		T35	1