Module Definition
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Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.08 100.00 84.31 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.63 100.00 74.51 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T18,T13
10CoveredT6,T11,T12
11CoveredT6,T18,T13

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T18,T13

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T18,T13
10CoveredT6,T12,T21
11CoveredT6,T18,T13

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T18,T13

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT6,T18,T13
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT6,T18,T13
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T11
10CoveredT1,T2,T3
11CoveredT2,T3,T11

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T11

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T36,T27
10CoveredT1,T2,T4
11CoveredT2,T36,T27

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T36,T27

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T11,T36
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T11,T36
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT75,T42,T180
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT75,T42,T180
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T75,T42,T180


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT52,T154,T211
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT52,T154,T211
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T52,T154,T211


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T4
0 0 0 1 Covered T2,T3,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T4
0 0 0 1 Covered T2,T3,T4
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT11,T12,T16
10CoveredT11,T12,T16
11CoveredT11,T12,T16

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT11,T12,T16
10CoveredT11,T12,T16
11CoveredT11,T12,T16

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT155,T70,T212
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT155,T70,T212
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T155,T70,T212


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T11,T12,T16
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T11,T12,T16
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT6,T11,T12
11CoveredT6,T11,T12

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT6,T11,T12
11CoveredT6,T11,T12

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT156,T213,T214
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT156,T213,T214
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T156,T213,T214


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T11,T12
0 0 0 1 Covered T6,T11,T12
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T11,T12
0 0 0 1 Covered T6,T11,T12
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T4
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T36,T172
10CoveredT1,T2,T4
11CoveredT2,T36,T172

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T36,T172

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T36,T172
10CoveredT1,T2,T4
11CoveredT2,T36,T172

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T36,T172

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T159,T75

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T159,T75

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T36,T172
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T36,T172
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T158,T159,T75
0 1 Covered T1,T2,T3
0 0 Covered T2,T36,T172


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T36,T172
0 0 0 1 Covered T1,T2,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T36,T172
0 0 0 1 Covered T1,T2,T4
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T4,T7
10CoveredT2,T4,T7
11CoveredT2,T4,T7

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T7

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T4,T7
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T4,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T74
0 1 Covered T1,T2,T3
0 0 Covered T2,T4,T7


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T4
0 0 0 1 Covered T2,T3,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T4,T7
0 0 0 1 Covered T2,T4,T7
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T74
10CoveredT2,T3,T74
11CoveredT2,T3,T74

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T58,T75
10CoveredT2,T58,T75
11CoveredT2,T58,T75

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T58,T75

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T74

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T58,T75
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T58,T75
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T74
0 1 Covered T1,T2,T3
0 0 Covered T2,T58,T75


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T74
0 0 0 1 Covered T2,T3,T74
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T58,T75
0 0 0 1 Covered T2,T58,T75
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT11,T12,T16
10CoveredT11,T12,T16
11CoveredT11,T12,T16

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT11,T12,T16
10CoveredT11,T12,T16
11CoveredT11,T12,T16

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T16

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT11,T12,T16
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT11,T12,T16
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T11,T12,T16
0 1 Covered T1,T2,T3
0 0 Covered T11,T12,T16


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T11,T12,T16
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T11,T12,T16
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT11,T27,T23
10CoveredT11,T12,T16
11CoveredT11,T27,T23

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T27,T23

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT27,T23,T29
10CoveredT11,T12,T16
11CoveredT27,T23,T13

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T23,T29

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T90,T91

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T90,T91

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT11,T27,T23
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT11,T27,T23
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T27,T90,T91
0 1 Covered T1,T2,T3
0 0 Covered T11,T27,T23


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T11,T27,T23
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T27,T23,T13
0 0 0 1 Covered T11,T12,T16
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT6,T11,T12
11CoveredT6,T11,T12

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T11,T12
10CoveredT6,T11,T12
11CoveredT6,T11,T12

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T11,T12

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT6,T11,T12
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT6,T11,T12
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T6,T11,T12
0 1 Covered T1,T2,T3
0 0 Covered T6,T11,T12


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T11,T12
0 0 0 1 Covered T6,T11,T12
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T11,T12
0 0 0 1 Covered T6,T11,T12
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T18,T13
10CoveredT6,T11,T12
11CoveredT6,T18,T13

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T18,T13

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT6,T18,T13
10CoveredT6,T12,T21
11CoveredT6,T18,T13

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T18,T13

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT6,T18,T13
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT6,T18,T13
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T15
0 1 Covered T1,T2,T3
0 0 Covered T6,T18,T13


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T18,T13
0 0 0 1 Covered T6,T11,T12
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T6,T18,T13
0 0 0 1 Covered T6,T12,T21
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%