Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	306632062	0	0	0
ctrl_rd_A	306632062	2487	0	0
host_fifo_config_rd_A	306632062	5931	0	0
host_nack_handler_timeout_rd_A	306632062	1312	0	0
host_timeout_ctrl_rd_A	306632062	1126	0	0
intr_enable_rd_A	306632062	5258	0	0
ovrd_rd_A	306632062	2292	0	0
target_fifo_config_rd_A	306632062	1269	0	0
target_id_rd_A	306632062	1736	0	0
target_timeout_ctrl_rd_A	306632062	1273	0	0
timeout_ctrl_rd_A	306632062	1595	0	0
timing0_rd_A	306632062	1201	0	0
timing1_rd_A	306632062	1197	0	0
timing2_rd_A	306632062	1216	0	0
timing3_rd_A	306632062	1257	0	0
timing4_rd_A	306632062	1314	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	2487	0	0
T92	7253	73	0	0
T93	1938	30	0	0
T94	3149	41	0	0
T95	1340	1	0	0
T96	3016	33	0	0
T97	3976	21	0	0
T98	14380	201	0	0
T99	152184	257	0	0
T100	3834	9	0	0
T101	3753	47	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	5931	0	0
T20	161315	0	0	0
T43	16239	0	0	0
T44	17418	0	0	0
T54	0	200	0	0
T70	149740	0	0	0
T81	0	413	0	0
T102	496015	206	0	0
T103	0	195	0	0
T104	0	108	0	0
T105	0	281	0	0
T106	0	205	0	0
T107	0	120	0	0
T108	0	235	0	0
T109	0	127	0	0
T110	37088	0	0	0
T111	60365	0	0	0
T112	91655	0	0	0
T113	16641	0	0	0
T114	45919	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1312	0	0
T92	7253	23	0	0
T93	1938	6	0	0
T94	3149	23	0	0
T95	1340	4	0	0
T96	3016	16	0	0
T97	3976	13	0	0
T98	14380	63	0	0
T99	152184	217	0	0
T100	3834	16	0	0
T101	3753	17	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1126	0	0
T92	7253	33	0	0
T93	1938	6	0	0
T94	3149	17	0	0
T96	3016	18	0	0
T97	3976	23	0	0
T98	14380	66	0	0
T99	152184	238	0	0
T100	3834	44	0	0
T101	3753	17	0	0
T115	1876	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	5258	0	0
T52	224587	16	0	0
T62	209588	0	0	0
T81	0	21	0	0
T108	0	16	0	0
T116	0	18	0	0
T117	0	12	0	0
T118	0	13	0	0
T119	0	10	0	0
T120	0	30	0	0
T121	0	17	0	0
T122	0	27	0	0
T123	141801	0	0	0
T124	203353	0	0	0
T125	222346	0	0	0
T126	32109	0	0	0
T127	140118	0	0	0
T128	824	0	0	0
T129	643042	0	0	0
T130	50150	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	2292	0	0
T47	34375	0	0	0
T48	288860	0	0	0
T131	2132	28	0	0
T132	0	24	0	0
T133	0	18	0	0
T134	0	61	0	0
T135	0	25	0	0
T136	0	52	0	0
T137	0	45	0	0
T138	0	85	0	0
T139	0	55	0	0
T140	0	64	0	0
T141	21384	0	0	0
T142	24184	0	0	0
T143	83897	0	0	0
T144	144464	0	0	0
T145	4111	0	0	0
T146	93730	0	0	0
T147	5839	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1269	0	0
T92	7253	16	0	0
T93	1938	10	0	0
T94	3149	17	0	0
T95	1340	4	0	0
T96	3016	20	0	0
T97	3976	32	0	0
T98	14380	30	0	0
T99	152184	219	0	0
T100	3834	9	0	0
T101	3753	33	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1736	0	0
T92	7253	56	0	0
T93	1938	9	0	0
T94	3149	27	0	0
T96	3016	6	0	0
T97	3976	45	0	0
T98	14380	100	0	0
T99	152184	215	0	0
T100	3834	36	0	0
T101	3753	20	0	0
T115	1876	2	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1273	0	0
T92	7253	26	0	0
T93	1938	2	0	0
T94	3149	20	0	0
T95	1340	2	0	0
T96	3016	32	0	0
T97	3976	16	0	0
T98	14380	75	0	0
T99	152184	210	0	0
T100	3834	1	0	0
T101	3753	6	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1595	0	0
T92	7253	40	0	0
T93	1938	9	0	0
T94	3149	19	0	0
T96	3016	30	0	0
T97	3976	22	0	0
T98	14380	73	0	0
T99	152184	198	0	0
T100	3834	18	0	0
T101	3753	42	0	0
T115	1876	13	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1201	0	0
T92	7253	20	0	0
T94	3149	28	0	0
T96	3016	34	0	0
T97	3976	23	0	0
T98	14380	42	0	0
T99	152184	202	0	0
T101	3753	18	0	0
T115	1876	9	0	0
T148	9503	10	0	0
T149	7564	18	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1197	0	0
T92	7253	35	0	0
T93	1938	3	0	0
T94	3149	31	0	0
T95	1340	4	0	0
T96	3016	8	0	0
T97	3976	13	0	0
T98	14380	36	0	0
T99	152184	207	0	0
T100	3834	24	0	0
T101	3753	24	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1216	0	0
T92	7253	31	0	0
T93	1938	3	0	0
T94	3149	31	0	0
T95	1340	4	0	0
T96	3016	48	0	0
T97	3976	18	0	0
T98	14380	71	0	0
T99	152184	209	0	0
T100	3834	42	0	0
T101	3753	19	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1257	0	0
T92	7253	23	0	0
T93	1938	11	0	0
T94	3149	31	0	0
T95	1340	2	0	0
T96	3016	16	0	0
T97	3976	17	0	0
T98	14380	84	0	0
T99	152184	219	0	0
T100	3834	44	0	0
T101	3753	7	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306632062	1314	0	0
T92	7253	27	0	0
T93	1938	12	0	0
T94	3149	39	0	0
T96	3016	4	0	0
T97	3976	8	0	0
T98	14380	73	0	0
T99	152184	232	0	0
T100	3834	28	0	0
T101	3753	26	0	0
T115	1876	9	0	0