Summary for Variable cp_sclval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_sclval
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
410 |
1 |
|
|
T2 |
10 |
|
T93 |
5 |
|
T94 |
10 |
auto[1] |
360 |
1 |
|
|
T2 |
7 |
|
T93 |
7 |
|
T94 |
7 |
Summary for Variable cp_sdaval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_sdaval
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
392 |
1 |
|
|
T2 |
7 |
|
T93 |
8 |
|
T94 |
6 |
auto[1] |
378 |
1 |
|
|
T2 |
10 |
|
T93 |
4 |
|
T94 |
11 |
Summary for Variable cp_txorvden
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_txorvden
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
393 |
1 |
|
|
T2 |
10 |
|
T93 |
7 |
|
T94 |
10 |
auto[1] |
377 |
1 |
|
|
T2 |
7 |
|
T93 |
5 |
|
T94 |
7 |
Summary for Cross cp_txorvden_x_sclval
Samples crossed: cp_txorvden cp_sclval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_txorvden_x_sclval
Bins
cp_txorvden | cp_sclval | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
204 |
1 |
|
|
T2 |
6 |
|
T93 |
1 |
|
T94 |
5 |
auto[0] |
auto[1] |
189 |
1 |
|
|
T2 |
4 |
|
T93 |
6 |
|
T94 |
5 |
auto[1] |
auto[0] |
206 |
1 |
|
|
T2 |
4 |
|
T93 |
4 |
|
T94 |
5 |
auto[1] |
auto[1] |
171 |
1 |
|
|
T2 |
3 |
|
T93 |
1 |
|
T94 |
2 |
Summary for Cross cp_txorvden_x_sdaval
Samples crossed: cp_txorvden cp_sdaval
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_txorvden_x_sdaval
Bins
cp_txorvden | cp_sdaval | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
207 |
1 |
|
|
T2 |
3 |
|
T93 |
3 |
|
T94 |
4 |
auto[0] |
auto[1] |
186 |
1 |
|
|
T2 |
7 |
|
T93 |
4 |
|
T94 |
6 |
auto[1] |
auto[0] |
185 |
1 |
|
|
T2 |
4 |
|
T93 |
5 |
|
T94 |
2 |
auto[1] |
auto[1] |
192 |
1 |
|
|
T2 |
3 |
|
T94 |
5 |
|
T298 |
8 |