Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.22	85.22	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_protocol_cov_cg	85.22	1	100	1	64	64

---

Group Instance : i2c_protocol_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.22	1	100	1	64	64

---

Summary for Group Instance i2c_protocol_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	47	8	39	82.98
Crosses	68	9	59	86.76

Variables for Group Instance i2c_protocol_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
RStart_before_read_data_ACK_cp	1	0	1	100.00	100	1	1	0
RStart_during_address_Ack_cp	1	0	1	100.00	100	1	1	0
RStart_during_address_transmission_cp	1	0	1	100.00	100	1	1	0
RStart_during_read_data_cp	1	0	1	100.00	100	1	1	0
RStart_during_rw_bit_cp	1	1	0	0.00	100	1	1	0
RStart_during_write_data_cp	1	0	1	100.00	100	1	1	0
Read_data_ack_before_stop_cp	1	1	0	0.00	100	1	1	0
Rstart_after_Address_Ack_cp	1	0	1	100.00	100	1	1	0
Rstart_after_Address_Nack_cp	1	0	1	100.00	100	1	1	0
Start_followed_by_Rstart_cp	1	0	1	100.00	100	1	1	2
Stop_after_read_data_Nack_cp	1	0	1	100.00	100	1	1	0
Stop_after_read_data_ack_cp	1	1	0	0.00	100	1	1	0
Stop_after_write_data_Nack_cp	1	1	0	0.00	100	1	1	0
Stop_after_write_data_ack_cp	1	0	1	100.00	100	1	1	0
Stop_without_ACK_after_addr_cp	1	1	0	0.00	100	1	1	0
Stop_without_ACK_after_data_cp	1	0	1	100.00	100	1	1	0
Stop_without_ACK_after_read_cp	1	1	0	0.00	100	1	1	0
Stop_without_ACK_after_write_cp	1	1	0	0.00	100	1	1	0
bus_state_cp	17	1	16	94.12	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0
num_rd_bytes_cp	5	0	5	100.00	100	1	1	0
num_wr_bytes_cp	5	0	5	100.00	100	1	1	0

Crosses for Group Instance i2c_protocol_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
bus_state_x_ip_mode_cp	34	3	31	91.18	100	1	1	0
num_rd_bytes_x_ip_mode_cp	10	0	10	100.00	100	1	1	0
num_wr_bytes_x_ip_mode_cp	10	0	10	100.00	100	1	1	0
Stop_after_write_data_ack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Stop_after_read_data_ack_x_ip_mode_cp	2	2	0	0.00	100	1	1	0
Stop_after_write_data_Nack_x_ip_mode_cp	2	2	0	0.00	100	1	1	0
Stop_after_read_data_Nack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Rstart_after_Address_Ack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Rstart_after_Address_Nack_x_ip_mode_cp	2	1	1	50.00	100	1	1	0
Start_followed_by_Rstart_cp_x_ip_mode_cp	2	1	1	50.00	100	1	1	0

Summary for Variable RStart_before_read_data_ACK_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_before_read_data_ACK_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Start_before_read_data_ACK_Nack

6441

1

T1

10

T3

1

T5

1

---

Summary for Variable RStart_during_address_Ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_address_Ack_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Start_during_address_Acknowledge	8	1			T49	4		T50	4

---

Summary for Variable RStart_during_address_transmission_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_address_transmission_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Start_during_address_transmission

4

1

T72

1

T73

1

T74

1

---

Summary for Variable RStart_during_read_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_read_data_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Start_during_read_data	24	1			T49	12		T50	12

---

Summary for Variable RStart_during_rw_bit_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Start_during_rw_bit	0	1	1

---

Summary for Variable RStart_during_write_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_write_data_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Start_during_write_data

11015

1

T1

15

T4

44

T7

9

---

Summary for Variable Read_data_ack_before_stop_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Read_data_ack_before_stop	0	1	1

---

Summary for Variable Rstart_after_Address_Ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Rstart_after_Address_Ack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Rstart_after_Address_Ack

31

1

T254

1

T255

1

T256

1

---

Summary for Variable Rstart_after_Address_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Rstart_after_Address_Nack_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Rstart_after_Address_Nack	8	1			T49	4		T50	4

---

Summary for Variable Start_followed_by_Rstart_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	2	1			T257	2

---

Summary for Variable Stop_after_read_data_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_after_read_data_Nack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_read_data_Nack

7433

1

T1

4

T6

9

T9

48

---

Summary for Variable Stop_after_read_data_ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_after_read_data_ack	0	1	1

---

Summary for Variable Stop_after_write_data_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_after_write_data_Nack_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_after_write_data_Nack	0	1	1

---

Summary for Variable Stop_after_write_data_ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_after_write_data_ack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_ack

4479

1

T1

3

T6

10

T52

4

---

Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_without_ACK_after_addr_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_without_ACK_after_addr	0	1	1

---

Summary for Variable Stop_without_ACK_after_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_without_ACK_after_data_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_without_ACK_after_data

2113

1

T1

3

T52

4

T67

19

---

Summary for Variable Stop_without_ACK_after_read_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_without_ACK_after_read	0	1	1

---

Summary for Variable Stop_without_ACK_after_write_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_without_ACK_after_write	0	1	1

---

Summary for Variable bus_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	1	16	94.12

User Defined Bins for bus_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_addr_nack	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
idle	306368	1			T1	6428		T2	3		T3	1
stop	12545	1			T1	14		T6	19		T9	48
write_data_nack	409	1			T4	4		T10	4		T51	4
write_data_ack	711253	1			T1	321		T4	739		T5	2
read_data_nack	55521	1			T1	50		T3	7		T5	3
read_data_ack	743758	1			T1	440		T3	204		T5	48
write_data	4888357	1			T1	2429		T4	5486		T5	28
read_data	5235672	1			T1	2966		T3	1264		T5	318
write_addr_nack	24	1			T49	4		T57	4		T50	4
write_addr_ack	55002	1			T1	61		T4	162		T5	3
read_addr_ack	48163	1			T1	51		T3	8		T5	3
write	65004	1			T1	72		T4	180		T5	4
read	43769	1			T1	45		T3	6		T5	3
addr	645857	1			T1	1683		T2	1		T3	47
rstart	47014	1			T1	124		T2	2		T3	3
start	34543	1			T1	30		T2	2		T3	2

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

6592436

1

T1

14714

T3

1542

T4

7510

host

6300823

1

T2

8

T6

8896

T9

28692

---

Summary for Variable num_rd_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for num_rd_bytes_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixtyfour	10639	1			T9	60		T14	58		T40	48
high	689677	1			T1	101		T3	227		T9	2456
mid	1336240	1			T1	540		T3	536		T6	1945
low	2997746	1			T1	2219		T3	618		T5	324
one	303030	1			T1	287		T3	50		T5	24

---

Summary for Variable num_wr_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for num_wr_bytes_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixtyfour	13947	1			T4	28		T7	26		T10	4
high	631354	1			T4	812		T7	548		T10	554
mid	1018787	1			T4	1236		T6	129		T7	614
low	2464397	1			T1	1876		T4	2350		T6	1380
one	297797	1			T1	413		T4	432		T5	3

---

Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	34	3	31	91.18	3

Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Element holes

bus_state_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[read_addr_nack]	*	--	--	2

Uncovered bins

bus_state_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[write_addr_nack]	[host]	0	1	1

Covered bins

bus_state_cp	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
idle	device	304176	1			T1	6428		T3	1		T4	1
idle	host	2192	1			T2	3		T6	1		T9	35
stop	device	4509	1			T1	14		T52	4		T67	39
stop	host	8036	1			T6	19		T9	48		T14	47
write_data_nack	device	396	1			T4	4		T10	4		T51	4
write_data_nack	host	13	1			T24	6		T258	7		-	-
write_data_ack	device	448272	1			T1	321		T4	739		T5	2
write_data_ack	host	262981	1			T6	276		T13	318		T41	391
read_data_nack	device	28839	1			T1	50		T3	7		T5	3
read_data_nack	host	26682	1			T6	40		T9	196		T14	192
read_data_ack	device	229512	1			T1	440		T3	204		T5	48
read_data_ack	host	514246	1			T6	777		T9	3292		T14	3338
write_data	device	3313057	1			T1	2429		T4	5486		T5	28
write_data	host	1575300	1			T6	1625		T13	1943		T41	2352
read_data	device	1546633	1			T1	2966		T3	1264		T5	318
read_data	host	3689039	1			T6	5635		T9	23848		T14	24144
write_addr_nack	device	24	1			T49	4		T57	4		T50	4
write_addr_ack	device	46077	1			T1	61		T4	162		T5	3
write_addr_ack	host	8925	1			T6	33		T13	4		T41	57
read_addr_ack	device	30976	1			T1	51		T3	8		T5	3
read_addr_ack	host	17187	1			T6	30		T9	147		T14	144
write	device	54464	1			T1	72		T4	180		T5	4
write	host	10540	1			T6	40		T13	4		T41	64
read	device	26550	1			T1	45		T3	6		T5	3
read	host	17219	1			T6	30		T9	147		T14	144
addr	device	498767	1			T1	1683		T3	47		T4	829
addr	host	147090	1			T2	1		T6	338		T9	858
rstart	device	46873	1			T1	124		T3	3		T4	106
rstart	host	141	1			T2	2		T15	3		T12	3
start	device	13311	1			T1	30		T3	2		T4	3
start	host	21232	1			T2	2		T6	52		T9	121

---

Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins

ip_mode_cp	num_rd_bytes_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
device	sixtyfour	1464	1			T259	26		T260	72		T261	24
device	high	55559	1			T1	101		T3	227		T69	79
device	mid	216209	1			T1	540		T3	536		T69	953
device	low	1134729	1			T1	2219		T3	618		T5	324
device	one	157566	1			T1	287		T3	50		T5	24
host	sixtyfour	9175	1			T9	60		T14	58		T40	48
host	high	634118	1			T9	2456		T14	1238		T40	6602
host	mid	1120031	1			T6	1945		T9	6567		T14	7651
host	low	1863017	1			T6	4049		T9	15545		T14	15673
host	one	145464	1			T6	288		T9	1259		T14	1179

---

Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins

ip_mode_cp	num_wr_bytes_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
device	sixtyfour	7744	1			T4	28		T7	26		T10	4
device	high	209234	1			T4	812		T7	548		T10	554
device	mid	492353	1			T4	1236		T7	614		T10	1002
device	low	1797602	1			T1	1876		T4	2350		T7	2211
device	one	244030	1			T1	413		T4	432		T5	3
host	sixtyfour	6203	1			T13	24		T40	60		T42	26
host	high	422120	1			T13	498		T40	5898		T42	492
host	mid	526434	1			T6	129		T13	536		T41	500
host	low	666795	1			T6	1380		T13	494		T41	1655
host	one	53767	1			T6	179		T13	26		T41	249

---

Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins

Stop_after_write_data_ack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_ack

device

2113

1

T1

3

T52

4

T67

19

Stop_after_write_data_ack

host

2366

1

T6

10

T41

16

T40

12

---

Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins

Stop_after_read_data_ack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2

---

Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Uncovered bins

Stop_after_write_data_Nack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2

---

Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins

Stop_after_read_data_Nack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_read_data_Nack

device

2049

1

T1

4

T67

20

T48

14

Stop_after_read_data_Nack

host

5384

1

T6

9

T9

48

T14

47

---

Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins

Rstart_after_Address_Ack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Rstart_after_Address_Ack

device

20

1

T49

10

T50

10

-

-

Rstart_after_Address_Ack

host

11

1

T254

1

T255

1

T256

1

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Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	1	1	50.00	1

Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Element holes

Rstart_after_Address_Nack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[host]	0	1	1

Covered bins

Rstart_after_Address_Nack_cp	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Rstart_after_Address_Nack	device	8	1			T49	4		T50	4

---

Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	1	1	50.00	1

Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes

Start_followed_by_Rstart_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[device]	0	1	1

Excluded/Illegal bins

Start_followed_by_Rstart_cp	ip_mode_cp	COUNT	STATUS
[auto[0]]	[device , host]	--	Excluded	(2 bins)

Covered bins

Start_followed_by_Rstart_cp	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	host	2	1			T257	2