Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18438910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4636570

1

T1

168

T2

14

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22614738	1			T1	488		T2	18		T3	70
values[0x0]	230600	1			T1	129		T2	6		T3	36
values[0x1]	230142	1			T1	121		T2	11		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12772379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10303101

1

T1

351

T2

16

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	93777	1			T1	1		T4	1		T5	3
valid_sources[0x01]	93056	1			T1	2		T3	1		T4	1
valid_sources[0x02]	85564	1			T3	1		T4	2		T5	2
valid_sources[0x03]	100316	1			T1	2		T4	2		T5	4
valid_sources[0x04]	90524	1			T1	1		T4	2		T5	6
valid_sources[0x05]	82045	1			T1	6		T3	1		T4	4
valid_sources[0x06]	78421	1			T1	6		T4	1		T6	120
valid_sources[0x07]	89680	1			T1	6		T4	4		T5	8
valid_sources[0x08]	97006	1			T1	2		T3	1		T4	1
valid_sources[0x09]	82800	1			T1	10		T3	1		T4	2
valid_sources[0x0a]	98747	1			T1	3		T3	1		T4	1
valid_sources[0x0b]	85341	1			T1	1		T4	4		T5	5
valid_sources[0x0c]	99035	1			T4	2		T5	2		T6	102
valid_sources[0x0d]	80433	1			T1	3		T4	1		T5	1
valid_sources[0x0e]	91907	1			T1	2		T3	2		T4	2
valid_sources[0x0f]	96184	1			T1	1		T3	1		T4	1
valid_sources[0x10]	83296	1			T1	7		T4	1		T5	7
valid_sources[0x11]	96028	1			T5	7		T6	80		T7	1
valid_sources[0x12]	90250	1			T1	3		T3	1		T4	1
valid_sources[0x13]	81363	1			T1	2		T5	4		T6	71
valid_sources[0x14]	92771	1			T4	1		T5	3		T6	117
valid_sources[0x15]	78302	1			T1	4		T4	1		T5	2
valid_sources[0x16]	97689	1			T1	10		T3	2		T5	5
valid_sources[0x17]	95089	1			T5	7		T6	112		T7	2
valid_sources[0x18]	84787	1			T1	1		T4	2		T5	8
valid_sources[0x19]	85774	1			T4	2		T5	1		T6	174
valid_sources[0x1a]	90146	1			T3	1		T4	4		T5	5
valid_sources[0x1b]	244327	1			T1	11		T3	1		T5	4
valid_sources[0x1c]	94162	1			T1	1		T3	1		T4	1
valid_sources[0x1d]	87084	1			T1	2		T3	1		T4	2
valid_sources[0x1e]	87043	1			T1	5		T3	1		T5	6
valid_sources[0x1f]	83520	1			T1	1		T3	1		T4	4
valid_sources[0x20]	79921	1			T3	1		T5	4		T6	60
valid_sources[0x21]	83637	1			T1	6		T5	4		T6	53
valid_sources[0x22]	81950	1			T1	3		T4	2		T5	2
valid_sources[0x23]	91373	1			T1	2		T3	1		T4	2
valid_sources[0x24]	94761	1			T3	2		T4	2		T5	3
valid_sources[0x25]	89415	1			T1	1		T3	2		T4	3
valid_sources[0x26]	78020	1			T1	3		T4	1		T5	5
valid_sources[0x27]	116325	1			T1	5		T3	2		T4	2
valid_sources[0x28]	82713	1			T3	1		T4	1		T5	3
valid_sources[0x29]	83918	1			T1	2		T5	3		T6	90
valid_sources[0x2a]	80869	1			T1	7		T4	4		T5	4
valid_sources[0x2b]	86353	1			T1	2		T4	3		T5	3
valid_sources[0x2c]	87944	1			T1	6		T3	1		T4	1
valid_sources[0x2d]	86123	1			T1	2		T4	1		T5	6
valid_sources[0x2e]	84013	1			T5	2		T6	105		T9	484
valid_sources[0x2f]	94629	1			T1	3		T3	1		T4	3
valid_sources[0x30]	82353	1			T4	3		T5	8		T6	100
valid_sources[0x31]	81552	1			T1	7		T4	1		T5	1
valid_sources[0x32]	84301	1			T4	1		T5	9		T6	73
valid_sources[0x33]	89507	1			T1	7		T3	2		T4	1
valid_sources[0x34]	91993	1			T1	1		T3	2		T4	1
valid_sources[0x35]	78196	1			T4	1		T5	4		T6	79
valid_sources[0x36]	86731	1			T1	16		T3	1		T5	5
valid_sources[0x37]	81244	1			T1	2		T3	1		T4	5
valid_sources[0x38]	81504	1			T1	6		T5	6		T6	24
valid_sources[0x39]	93127	1			T3	1		T4	1		T5	2
valid_sources[0x3a]	84256	1			T3	1		T5	9		T6	85
valid_sources[0x3b]	89805	1			T4	3		T5	10		T6	145
valid_sources[0x3c]	94127	1			T1	6		T3	4		T4	3
valid_sources[0x3d]	85916	1			T1	3		T4	5		T5	4
valid_sources[0x3e]	80616	1			T4	2		T5	2		T6	116
valid_sources[0x3f]	78715	1			T1	1		T3	1		T4	1
valid_sources[0x40]	96326	1			T3	1		T4	2		T5	7
valid_sources[0x41]	88407	1			T1	1		T4	2		T5	3
valid_sources[0x42]	96940	1			T1	3		T4	1		T5	2
valid_sources[0x43]	90069	1			T4	3		T5	6		T6	141
valid_sources[0x44]	92523	1			T1	1		T3	1		T5	3
valid_sources[0x45]	87969	1			T4	1		T5	8		T6	73
valid_sources[0x46]	136905	1			T1	5		T3	1		T5	6
valid_sources[0x47]	90519	1			T1	17		T3	1		T4	2
valid_sources[0x48]	88649	1			T1	1		T5	4		T6	67
valid_sources[0x49]	84329	1			T5	9		T6	130		T7	1
valid_sources[0x4a]	87358	1			T4	1		T5	7		T6	74
valid_sources[0x4b]	87099	1			T1	3		T3	1		T5	1
valid_sources[0x4c]	90452	1			T5	8		T6	121		T7	7
valid_sources[0x4d]	75332	1			T1	1		T3	1		T4	2
valid_sources[0x4e]	80028	1			T1	2		T3	1		T4	1
valid_sources[0x4f]	90041	1			T1	1		T5	4		T6	88
valid_sources[0x50]	109173	1			T1	3		T3	1		T4	2
valid_sources[0x51]	92484	1			T1	6		T3	2		T4	3
valid_sources[0x52]	92798	1			T1	4		T4	1		T5	4
valid_sources[0x53]	88612	1			T1	2		T3	1		T4	1
valid_sources[0x54]	98214	1			T3	2		T4	3		T5	6
valid_sources[0x55]	88084	1			T1	1		T3	2		T4	3
valid_sources[0x56]	90225	1			T1	1		T3	1		T5	4
valid_sources[0x57]	88540	1			T1	3		T5	6		T6	105
valid_sources[0x58]	88085	1			T1	1		T4	2		T5	4
valid_sources[0x59]	82417	1			T1	2		T4	1		T5	3
valid_sources[0x5a]	89444	1			T1	2		T4	1		T5	5
valid_sources[0x5b]	79725	1			T1	3		T3	2		T5	3
valid_sources[0x5c]	94265	1			T1	2		T4	1		T5	1
valid_sources[0x5d]	82770	1			T1	1		T3	1		T4	1
valid_sources[0x5e]	79804	1			T1	1		T3	3		T5	10
valid_sources[0x5f]	108221	1			T1	11		T2	10		T3	1
valid_sources[0x60]	81065	1			T5	8		T6	144		T7	2
valid_sources[0x61]	88341	1			T1	1		T5	1		T6	53
valid_sources[0x62]	87280	1			T3	2		T4	1		T5	2
valid_sources[0x63]	89390	1			T1	1		T6	125		T7	4
valid_sources[0x64]	89772	1			T1	8		T4	1		T5	4
valid_sources[0x65]	91836	1			T1	4		T4	2		T5	2
valid_sources[0x66]	78528	1			T4	3		T5	4		T6	120
valid_sources[0x67]	84921	1			T4	2		T5	5		T6	128
valid_sources[0x68]	108935	1			T1	2		T3	2		T4	1
valid_sources[0x69]	104005	1			T1	8		T5	5		T6	125
valid_sources[0x6a]	90204	1			T1	3		T4	2		T5	2
valid_sources[0x6b]	84810	1			T1	1		T5	6		T6	158
valid_sources[0x6c]	93037	1			T1	9		T4	2		T5	5
valid_sources[0x6d]	183124	1			T1	7		T3	1		T5	5
valid_sources[0x6e]	160157	1			T1	4		T5	1		T6	104
valid_sources[0x6f]	80755	1			T1	3		T4	4		T5	8
valid_sources[0x70]	79738	1			T3	1		T4	2		T5	6
valid_sources[0x71]	101027	1			T1	3		T4	1		T5	11
valid_sources[0x72]	88748	1			T1	6		T5	3		T6	140
valid_sources[0x73]	82633	1			T1	2		T4	1		T5	2
valid_sources[0x74]	83553	1			T1	3		T5	9		T6	126
valid_sources[0x75]	78815	1			T3	1		T4	1		T5	5
valid_sources[0x76]	86042	1			T3	2		T5	2		T6	112
valid_sources[0x77]	84405	1			T1	4		T5	10		T6	87
valid_sources[0x78]	81791	1			T1	7		T3	1		T4	1
valid_sources[0x79]	230735	1			T1	2		T3	1		T4	2
valid_sources[0x7a]	81876	1			T1	1		T3	2		T5	10
valid_sources[0x7b]	85736	1			T1	1		T4	1		T5	6
valid_sources[0x7c]	81883	1			T1	3		T3	2		T4	2
valid_sources[0x7d]	79243	1			T1	5		T3	2		T4	1
valid_sources[0x7e]	86593	1			T1	4		T3	1		T5	6
valid_sources[0x7f]	82090	1			T1	1		T5	12		T6	53
valid_sources[0x80]	87547	1			T1	2		T3	2		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4409007

1

T1

79

T2

11

T3

2

values[0x0]

all_enables

biggest_size

130856

1

T1

56

T2

2

T3

14

values[0x1]

all_enables

biggest_size

96707

1

T1

33

T2

1

T3

14