Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40616

1

T1

16

T2

12

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32404	1			T1	20		T2	11		T3	11
values[0x0]	15553	1			T1	10		T2	7		T3	9
values[0x1]	16548	1			T1	10		T2	4		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47742

1

T1

20

T2

15

T3

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	360	1			T6	5		T22	1		T8	16
valid_sources[0x01]	265	1			T4	1		T10	1		T6	3
valid_sources[0x02]	396	1			T4	3		T7	1		T5	16
valid_sources[0x03]	334	1			T4	3		T10	1		T26	1
valid_sources[0x04]	327	1			T10	1		T26	3		T15	1
valid_sources[0x05]	232	1			T4	4		T10	1		T8	5
valid_sources[0x06]	387	1			T4	3		T26	2		T28	129
valid_sources[0x07]	147	1			T4	2		T11	1		T21	2
valid_sources[0x08]	189	1			T7	1		T10	1		T22	1
valid_sources[0x09]	170	1			T4	4		T7	2		T10	3
valid_sources[0x0a]	393	1			T22	1		T9	1		T28	128
valid_sources[0x0b]	400	1			T4	5		T5	10		T10	3
valid_sources[0x0c]	172	1			T4	2		T26	1		T15	1
valid_sources[0x0d]	186	1			T4	1		T5	6		T22	1
valid_sources[0x0e]	343	1			T4	1		T22	1		T8	2
valid_sources[0x0f]	206	1			T4	4		T10	2		T22	2
valid_sources[0x10]	205	1			T4	3		T10	1		T8	7
valid_sources[0x11]	236	1			T4	1		T7	1		T22	3
valid_sources[0x12]	376	1			T4	5		T7	1		T5	8
valid_sources[0x13]	195	1			T4	1		T10	2		T22	4
valid_sources[0x14]	286	1			T2	3		T4	1		T7	1
valid_sources[0x15]	202	1			T4	4		T21	1		T22	1
valid_sources[0x16]	240	1			T5	1		T11	1		T10	1
valid_sources[0x17]	196	1			T4	2		T10	8		T8	4
valid_sources[0x18]	209	1			T4	1		T10	1		T22	2
valid_sources[0x19]	229	1			T4	1		T7	1		T10	3
valid_sources[0x1a]	183	1			T4	5		T7	4		T5	7
valid_sources[0x1b]	241	1			T4	3		T10	1		T22	3
valid_sources[0x1c]	235	1			T4	2		T10	7		T22	5
valid_sources[0x1d]	160	1			T4	2		T8	1		T14	15
valid_sources[0x1e]	194	1			T4	1		T10	3		T22	1
valid_sources[0x1f]	207	1			T4	2		T7	2		T8	2
valid_sources[0x20]	312	1			T4	1		T5	6		T10	1
valid_sources[0x21]	333	1			T4	8		T5	4		T8	2
valid_sources[0x22]	275	1			T22	2		T9	2		T30	37
valid_sources[0x23]	307	1			T4	6		T5	12		T6	6
valid_sources[0x24]	215	1			T4	3		T22	6		T15	2
valid_sources[0x25]	212	1			T4	1		T10	2		T8	4
valid_sources[0x26]	168	1			T4	2		T21	1		T22	5
valid_sources[0x27]	244	1			T7	3		T5	7		T10	1
valid_sources[0x28]	198	1			T4	1		T5	7		T10	1
valid_sources[0x29]	257	1			T4	5		T7	1		T5	4
valid_sources[0x2a]	247	1			T4	2		T22	8		T8	9
valid_sources[0x2b]	363	1			T4	2		T10	2		T22	3
valid_sources[0x2c]	225	1			T3	1		T4	2		T6	1
valid_sources[0x2d]	200	1			T1	40		T4	3		T22	3
valid_sources[0x2e]	169	1			T7	1		T11	2		T10	2
valid_sources[0x2f]	287	1			T4	1		T5	15		T22	1
valid_sources[0x30]	186	1			T4	1		T10	3		T22	2
valid_sources[0x31]	225	1			T4	1		T10	1		T22	5
valid_sources[0x32]	316	1			T4	4		T6	1		T22	4
valid_sources[0x33]	307	1			T4	4		T22	3		T8	4
valid_sources[0x34]	359	1			T4	9		T22	3		T8	12
valid_sources[0x35]	169	1			T4	4		T7	3		T22	4
valid_sources[0x36]	182	1			T4	2		T7	1		T10	4
valid_sources[0x37]	270	1			T10	2		T22	3		T8	1
valid_sources[0x38]	257	1			T4	6		T22	2		T8	8
valid_sources[0x39]	368	1			T4	12		T22	3		T28	124
valid_sources[0x3a]	186	1			T4	2		T10	1		T22	4
valid_sources[0x3b]	210	1			T3	1		T4	8		T9	5
valid_sources[0x3c]	352	1			T4	2		T8	7		T26	1
valid_sources[0x3d]	219	1			T4	1		T13	22		T8	2
valid_sources[0x3e]	291	1			T4	2		T5	13		T8	2
valid_sources[0x3f]	250	1			T10	2		T16	3		T17	3
valid_sources[0x40]	186	1			T4	5		T7	1		T10	2
valid_sources[0x41]	234	1			T4	2		T8	15		T14	2
valid_sources[0x42]	283	1			T4	4		T10	1		T8	4
valid_sources[0x43]	176	1			T11	2		T10	1		T21	1
valid_sources[0x44]	429	1			T4	1		T7	1		T10	7
valid_sources[0x45]	207	1			T4	1		T22	1		T26	1
valid_sources[0x46]	329	1			T4	1		T7	1		T22	1
valid_sources[0x47]	230	1			T4	2		T10	3		T6	1
valid_sources[0x48]	271	1			T3	2		T4	1		T7	1
valid_sources[0x49]	478	1			T4	3		T22	8		T8	7
valid_sources[0x4a]	172	1			T4	2		T22	3		T9	1
valid_sources[0x4b]	228	1			T4	4		T27	1		T30	2
valid_sources[0x4c]	432	1			T4	3		T10	3		T8	2
valid_sources[0x4d]	174	1			T3	2		T4	1		T10	2
valid_sources[0x4e]	312	1			T4	1		T10	2		T22	7
valid_sources[0x4f]	429	1			T4	2		T10	5		T22	1
valid_sources[0x50]	223	1			T4	2		T10	1		T22	7
valid_sources[0x51]	266	1			T4	1		T22	1		T9	2
valid_sources[0x52]	253	1			T22	4		T8	4		T26	1
valid_sources[0x53]	321	1			T4	2		T9	7		T14	10
valid_sources[0x54]	332	1			T4	2		T7	1		T5	1
valid_sources[0x55]	202	1			T3	1		T4	5		T10	1
valid_sources[0x56]	210	1			T3	1		T4	1		T10	4
valid_sources[0x57]	216	1			T4	2		T7	1		T11	1
valid_sources[0x58]	442	1			T4	4		T5	1		T10	3
valid_sources[0x59]	359	1			T4	6		T10	7		T8	2
valid_sources[0x5a]	258	1			T4	2		T5	6		T12	3
valid_sources[0x5b]	307	1			T4	2		T11	2		T10	2
valid_sources[0x5c]	225	1			T4	1		T10	1		T8	7
valid_sources[0x5d]	278	1			T10	4		T22	4		T8	4
valid_sources[0x5e]	187	1			T3	1		T4	5		T5	18
valid_sources[0x5f]	185	1			T4	2		T7	1		T22	2
valid_sources[0x60]	302	1			T4	1		T7	1		T22	2
valid_sources[0x61]	167	1			T10	2		T21	2		T22	5
valid_sources[0x62]	165	1			T4	4		T22	1		T8	2
valid_sources[0x63]	206	1			T21	1		T26	2		T9	2
valid_sources[0x64]	252	1			T4	2		T5	39		T22	8
valid_sources[0x65]	304	1			T5	6		T11	1		T8	6
valid_sources[0x66]	352	1			T4	7		T5	10		T8	5
valid_sources[0x67]	219	1			T4	1		T5	11		T11	2
valid_sources[0x68]	160	1			T10	1		T22	2		T29	1
valid_sources[0x69]	172	1			T4	3		T22	9		T9	6
valid_sources[0x6a]	287	1			T2	1		T4	3		T10	3
valid_sources[0x6b]	247	1			T4	1		T11	1		T10	1
valid_sources[0x6c]	176	1			T4	4		T10	2		T8	4
valid_sources[0x6d]	226	1			T4	2		T12	12		T22	4
valid_sources[0x6e]	395	1			T4	1		T21	1		T8	4
valid_sources[0x6f]	233	1			T10	1		T8	5		T14	40
valid_sources[0x70]	161	1			T4	4		T7	1		T5	1
valid_sources[0x71]	204	1			T4	1		T5	28		T22	4
valid_sources[0x72]	157	1			T26	2		T29	4		T14	2
valid_sources[0x73]	273	1			T4	4		T7	1		T5	16
valid_sources[0x74]	237	1			T22	2		T8	2		T29	43
valid_sources[0x75]	168	1			T4	3		T8	7		T9	3
valid_sources[0x76]	219	1			T10	4		T8	7		T9	2
valid_sources[0x77]	176	1			T4	1		T10	1		T6	1
valid_sources[0x78]	206	1			T4	5		T10	1		T22	2
valid_sources[0x79]	249	1			T3	1		T4	3		T5	25
valid_sources[0x7a]	236	1			T4	4		T5	5		T10	1
valid_sources[0x7b]	482	1			T4	6		T5	6		T22	5
valid_sources[0x7c]	220	1			T4	5		T7	2		T10	2
valid_sources[0x7d]	321	1			T4	6		T10	3		T22	1
valid_sources[0x7e]	262	1			T4	2		T7	1		T5	43
valid_sources[0x7f]	165	1			T4	4		T22	2		T14	1
valid_sources[0x80]	166	1			T4	1		T7	2		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14722

1

T1

9

T2

7

T3

5

values[0x0]

all_enables

biggest_size

13260

1

T1

5

T2

3

T3

3

values[0x1]

all_enables

biggest_size

12634

1

T1

2

T2

2

T4

112