Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	660707	0	0	0
ctrl_rd_A	660707	2685	0	0
host_fifo_config_rd_A	660707	1474	0	0
host_nack_handler_timeout_rd_A	660707	1453	0	0
host_timeout_ctrl_rd_A	660707	1246	0	0
intr_enable_rd_A	660707	4335	0	0
ovrd_rd_A	660707	1746	0	0
target_fifo_config_rd_A	660707	1402	0	0
target_id_rd_A	660707	1909	0	0
target_timeout_ctrl_rd_A	660707	1419	0	0
timeout_ctrl_rd_A	660707	1747	0	0
timing0_rd_A	660707	1565	0	0
timing1_rd_A	660707	1410	0	0
timing2_rd_A	660707	1444	0	0
timing3_rd_A	660707	1417	0	0
timing4_rd_A	660707	1481	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	2685	0	0
T4	6484	68	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	119	0	0
T15	0	24	0	0
T17	0	30	0	0
T18	0	8	0	0
T20	0	239	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	136	0	0
T37	0	15	0	0
T38	0	16	0	0
T51	0	240	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1474	0	0
T4	6484	12	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	46	0	0
T15	0	17	0	0
T17	0	8	0	0
T18	0	6	0	0
T20	0	115	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	39	0	0
T37	0	39	0	0
T38	0	11	0	0
T51	0	48	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1453	0	0
T4	6484	17	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	19	0	0
T15	0	12	0	0
T17	0	13	0	0
T18	0	14	0	0
T20	0	136	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	43	0	0
T37	0	49	0	0
T38	0	10	0	0
T51	0	28	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1246	0	0
T4	6484	20	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	25	0	0
T15	0	17	0	0
T17	0	17	0	0
T18	0	11	0	0
T20	0	87	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	35	0	0
T37	0	14	0	0
T38	0	5	0	0
T51	0	49	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	4335	0	0
T4	6484	142	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	180	0	0
T15	0	16	0	0
T17	0	6	0	0
T21	1185	8	0	0
T22	4071	0	0	0
T27	0	10	0	0
T29	0	229	0	0
T34	0	2	0	0
T37	0	22	0	0
T52	0	26	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1746	0	0
T4	6484	31	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	37	0	0
T15	0	2	0	0
T17	0	24	0	0
T18	0	16	0	0
T20	0	138	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	72	0	0
T37	0	29	0	0
T38	0	1	0	0
T51	0	117	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1402	0	0
T4	6484	37	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	28	0	0
T15	0	29	0	0
T17	0	9	0	0
T18	0	3	0	0
T20	0	131	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	46	0	0
T37	0	1	0	0
T38	0	9	0	0
T51	0	51	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1909	0	0
T4	6484	52	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	39	0	0
T15	0	9	0	0
T17	0	12	0	0
T18	0	25	0	0
T20	0	154	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	78	0	0
T37	0	51	0	0
T51	0	84	0	0
T53	0	28	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1419	0	0
T4	6484	16	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	37	0	0
T15	0	9	0	0
T17	0	25	0	0
T18	0	8	0	0
T20	0	100	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	47	0	0
T37	0	17	0	0
T38	0	5	0	0
T51	0	46	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1747	0	0
T4	6484	47	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	35	0	0
T15	0	10	0	0
T18	0	35	0	0
T20	0	139	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	77	0	0
T37	0	9	0	0
T38	0	10	0	0
T51	0	56	0	0
T53	0	39	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1565	0	0
T4	6484	28	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	41	0	0
T15	0	16	0	0
T17	0	10	0	0
T18	0	18	0	0
T20	0	174	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	41	0	0
T37	0	5	0	0
T38	0	14	0	0
T51	0	61	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1410	0	0
T4	6484	52	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	20	0	0
T15	0	13	0	0
T17	0	7	0	0
T18	0	20	0	0
T20	0	99	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	68	0	0
T37	0	21	0	0
T38	0	4	0	0
T51	0	34	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1444	0	0
T4	6484	21	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	28	0	0
T15	0	31	0	0
T17	0	21	0	0
T18	0	17	0	0
T20	0	100	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	81	0	0
T37	0	26	0	0
T38	0	6	0	0
T51	0	39	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1417	0	0
T4	6484	54	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	14	0	0
T15	0	4	0	0
T17	0	27	0	0
T18	0	7	0	0
T20	0	130	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	47	0	0
T37	0	11	0	0
T38	0	1	0	0
T51	0	60	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660707	1481	0	0
T4	6484	26	0	0
T5	4238	0	0	0
T6	1768	0	0	0
T7	1566	0	0	0
T10	2203	0	0	0
T11	1452	0	0	0
T12	1300	0	0	0
T13	1595	0	0	0
T14	0	33	0	0
T15	0	19	0	0
T17	0	5	0	0
T18	0	11	0	0
T20	0	127	0	0
T21	1185	0	0	0
T22	4071	0	0	0
T29	0	66	0	0
T37	0	33	0	0
T51	0	45	0	0
T53	0	56	0	0