Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 85.71 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_rd_wr_cg 85.71 1 100 1 64 64



Group Instance : i2c_rd_wr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64



Summary for Group Instance i2c_rd_wr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 2 16 88.89
Crosses 24 4 20 83.33


Variables for Group Instance i2c_rd_wr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
address_match 2 0 2 100.00 100 1 1 2
cp_address_match 4 0 4 100.00 100 1 1 0
cp_read_byte 5 1 4 80.00 100 1 1 0
cp_write_byte 5 1 4 80.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_rd_wr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_address_match_x_ip_mode 4 0 4 100.00 100 1 1 0
cross_write_byte_x_ip_mode 10 2 8 80.00 100 1 1 0
cross_read_byte_x_ip_mode 10 2 8 80.00 100 1 1 0


Summary for Variable address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for address_match

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12219271 1 T2 95320 T3 16269 T5 3828
auto[1] 11768799 1 T1 2188 T2 4562 T3 809


Summary for Variable cp_address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_address_match

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_addr_no_match 4095763 1 T2 41844 T3 7043 T6 1338
read_addr_match 6618353 1 T2 2104 T3 368 T6 42
write_addr_no_match 7835548 1 T2 53458 T3 9204 T5 3810
write_addr_match 5122595 1 T1 2168 T2 2452 T3 440


Summary for Variable cp_read_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_read_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 2192520 1 T2 9546 T3 1602 T6 316
med 4128460 1 T2 16607 T3 2964 T6 352
low 4273271 1 T2 17425 T3 2762 T6 709
all_zero 119865 1 T2 370 T3 83 T6 3


Summary for Variable cp_write_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_write_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 2635265 1 T1 462 T2 10743 T3 1729
med 5041000 1 T1 867 T2 21734 T3 4297
low 5157391 1 T1 823 T2 23092 T3 3580
all_zero 124487 1 T1 16 T2 341 T3 38


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12994425 1 T2 99882 T3 17078 T5 3916
host 10993645 1 T1 2188 T4 2192 T9 8


Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins
address_matchip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] device 12219166 1 T2 95320 T3 16269 T5 3828
auto[0] host 105 1 T210 3 T97 2 T176 2
auto[1] device 775259 1 T2 4562 T3 809 T5 88
auto[1] host 10993540 1 T1 2188 T4 2192 T9 8


Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1686706 1 T2 10743 T3 1729 T5 765
high host 948559 1 T1 462 T4 391 T35 3146
med device 3223784 1 T2 21734 T3 4297 T5 1534
med host 1817216 1 T1 867 T4 998 T18 97
low device 3309238 1 T2 23092 T3 3580 T5 1566
low host 1848153 1 T1 823 T4 752 T35 6530
all_zero device 77789 1 T2 341 T3 38 T5 27
all_zero host 46698 1 T1 16 T4 31 T18 47


Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1686706 1 T2 10743 T3 1729 T5 765
high host 948559 1 T1 462 T4 391 T35 3146
med device 3223784 1 T2 21734 T3 4297 T5 1534
med host 1817216 1 T1 867 T4 998 T18 97
low device 3309238 1 T2 23092 T3 3580 T5 1566
low host 1848153 1 T1 823 T4 752 T35 6530
all_zero device 77789 1 T2 341 T3 38 T5 27
all_zero host 46698 1 T1 16 T4 31 T18 47

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