Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29752282	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7553972

1

T1

1026

T2

2060

T3

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36480679	1			T1	2652		T2	5359		T3	911
values[0x0]	412605	1			T1	55		T2	1200		T3	212
values[0x1]	412970	1			T1	48		T2	1182		T3	231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20774027	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16532227

1

T1

1458

T2

3603

T3

656

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	135201	1			T1	6		T2	18		T3	7
valid_sources[0x01]	143543	1			T1	13		T2	22		T3	5
valid_sources[0x02]	147244	1			T1	18		T2	77		T3	11
valid_sources[0x03]	133734	1			T1	16		T2	25		T3	3
valid_sources[0x04]	155223	1			T1	14		T2	19		T3	4
valid_sources[0x05]	149903	1			T1	13		T2	44		T3	10
valid_sources[0x06]	136748	1			T1	5		T2	41		T3	2
valid_sources[0x07]	149143	1			T1	11		T2	34		T3	4
valid_sources[0x08]	140844	1			T1	20		T2	39		T3	2
valid_sources[0x09]	142342	1			T1	11		T2	30		T3	9
valid_sources[0x0a]	154517	1			T1	9		T2	23		T3	11
valid_sources[0x0b]	147259	1			T1	8		T2	41		T3	6
valid_sources[0x0c]	143677	1			T1	15		T2	36		T3	8
valid_sources[0x0d]	144500	1			T1	16		T2	29		T3	10
valid_sources[0x0e]	138920	1			T1	12		T2	18		T3	4
valid_sources[0x0f]	137960	1			T1	8		T2	25		T3	4
valid_sources[0x10]	137031	1			T1	10		T2	16		T3	4
valid_sources[0x11]	155350	1			T1	19		T2	54		T3	1
valid_sources[0x12]	150277	1			T1	14		T2	40		T3	9
valid_sources[0x13]	137995	1			T1	11		T2	50		T3	9
valid_sources[0x14]	143029	1			T1	5		T2	33		T3	5
valid_sources[0x15]	146812	1			T1	12		T2	26		T3	5
valid_sources[0x16]	143408	1			T1	9		T2	23		T3	6
valid_sources[0x17]	148705	1			T1	5		T2	37		T3	6
valid_sources[0x18]	148649	1			T1	6		T2	27		T3	6
valid_sources[0x19]	136660	1			T1	3		T2	15		T3	3
valid_sources[0x1a]	141362	1			T1	10		T2	42		T3	5
valid_sources[0x1b]	147068	1			T1	9		T2	35		T3	12
valid_sources[0x1c]	143072	1			T1	9		T2	22		T3	5
valid_sources[0x1d]	135224	1			T1	24		T2	40		T3	2
valid_sources[0x1e]	143272	1			T1	20		T2	61		T3	4
valid_sources[0x1f]	148454	1			T1	12		T2	48		T3	5
valid_sources[0x20]	148032	1			T1	11		T2	5		T3	9
valid_sources[0x21]	154614	1			T1	12		T2	7		T3	2
valid_sources[0x22]	147894	1			T1	13		T2	24		T3	6
valid_sources[0x23]	157530	1			T1	16		T2	38		T3	3
valid_sources[0x24]	139819	1			T1	11		T2	22		T3	3
valid_sources[0x25]	145144	1			T1	16		T2	34		T3	8
valid_sources[0x26]	144391	1			T1	17		T2	14		T3	3
valid_sources[0x27]	136509	1			T1	8		T2	37		T3	5
valid_sources[0x28]	156960	1			T1	8		T2	19		T3	3
valid_sources[0x29]	149954	1			T1	9		T2	22		T3	6
valid_sources[0x2a]	152338	1			T1	13		T2	33		T3	6
valid_sources[0x2b]	150120	1			T1	16		T2	16		T3	5
valid_sources[0x2c]	148475	1			T1	5		T2	50		T3	3
valid_sources[0x2d]	138110	1			T1	7		T2	27		T3	4
valid_sources[0x2e]	136792	1			T1	31		T2	16		T3	3
valid_sources[0x2f]	152070	1			T1	6		T2	55		T3	1
valid_sources[0x30]	145292	1			T1	13		T2	13		T3	2
valid_sources[0x31]	144910	1			T1	3		T2	35		T3	3
valid_sources[0x32]	142183	1			T1	12		T2	35		T3	7
valid_sources[0x33]	154821	1			T1	11		T2	63		T3	2
valid_sources[0x34]	140513	1			T1	16		T2	22		T3	3
valid_sources[0x35]	142898	1			T1	7		T2	33		T3	3
valid_sources[0x36]	140200	1			T1	9		T2	10		T3	3
valid_sources[0x37]	142370	1			T1	15		T2	38		T3	4
valid_sources[0x38]	150528	1			T1	10		T2	33		T3	8
valid_sources[0x39]	177593	1			T1	4		T2	24		T3	8
valid_sources[0x3a]	130034	1			T1	12		T2	45		T3	4
valid_sources[0x3b]	143033	1			T1	4		T2	40		T3	4
valid_sources[0x3c]	129275	1			T2	23		T3	7		T4	15
valid_sources[0x3d]	135342	1			T1	9		T2	74		T3	7
valid_sources[0x3e]	158529	1			T1	26		T2	36		T3	3
valid_sources[0x3f]	135446	1			T1	8		T2	24		T3	3
valid_sources[0x40]	137096	1			T1	8		T2	40		T3	1
valid_sources[0x41]	149059	1			T1	9		T2	20		T3	15
valid_sources[0x42]	148520	1			T1	1		T2	17		T3	7
valid_sources[0x43]	144481	1			T1	2		T2	15		T3	12
valid_sources[0x44]	149852	1			T1	15		T2	37		T3	5
valid_sources[0x45]	143830	1			T1	9		T2	30		T3	7
valid_sources[0x46]	132244	1			T1	8		T2	24		T3	7
valid_sources[0x47]	140908	1			T1	10		T2	36		T3	2
valid_sources[0x48]	150229	1			T1	14		T2	47		T3	3
valid_sources[0x49]	135303	1			T1	11		T2	26		T3	2
valid_sources[0x4a]	139976	1			T1	6		T2	42		T3	5
valid_sources[0x4b]	153052	1			T1	2		T2	73		T3	5
valid_sources[0x4c]	156293	1			T1	9		T2	7		T3	2
valid_sources[0x4d]	145355	1			T1	18		T2	18		T3	11
valid_sources[0x4e]	150271	1			T1	5		T2	21		T3	7
valid_sources[0x4f]	177645	1			T1	21		T2	31		T3	5
valid_sources[0x50]	163816	1			T1	6		T2	21		T3	4
valid_sources[0x51]	139137	1			T1	14		T2	41		T3	4
valid_sources[0x52]	158166	1			T1	26		T2	25		T3	8
valid_sources[0x53]	136432	1			T1	16		T2	9		T3	5
valid_sources[0x54]	139326	1			T1	5		T2	23		T3	7
valid_sources[0x55]	133176	1			T1	3		T2	29		T3	2
valid_sources[0x56]	171539	1			T1	7		T2	67		T3	8
valid_sources[0x57]	133007	1			T1	8		T2	49		T3	4
valid_sources[0x58]	145775	1			T1	12		T2	22		T3	14
valid_sources[0x59]	142558	1			T1	8		T2	31		T3	2
valid_sources[0x5a]	140686	1			T1	13		T2	27		T3	2
valid_sources[0x5b]	143602	1			T1	17		T2	59		T3	7
valid_sources[0x5c]	140673	1			T1	23		T2	42		T3	8
valid_sources[0x5d]	132841	1			T1	11		T2	42		T3	2
valid_sources[0x5e]	131167	1			T1	8		T2	13		T3	3
valid_sources[0x5f]	156393	1			T1	17		T2	19		T3	8
valid_sources[0x60]	133848	1			T1	14		T2	6		T3	6
valid_sources[0x61]	138071	1			T1	6		T2	6		T3	3
valid_sources[0x62]	154842	1			T1	14		T2	9		T3	1
valid_sources[0x63]	140430	1			T1	6		T2	38		T3	2
valid_sources[0x64]	154174	1			T1	20		T2	36		T3	2
valid_sources[0x65]	163036	1			T1	6		T2	28		T3	5
valid_sources[0x66]	144380	1			T1	5		T2	11		T3	5
valid_sources[0x67]	140427	1			T1	13		T2	53		T3	9
valid_sources[0x68]	142166	1			T1	27		T2	13		T3	6
valid_sources[0x69]	156451	1			T1	6		T2	32		T4	12
valid_sources[0x6a]	149656	1			T1	10		T2	26		T3	7
valid_sources[0x6b]	138209	1			T1	6		T2	25		T3	3
valid_sources[0x6c]	143366	1			T1	21		T2	35		T3	3
valid_sources[0x6d]	167571	1			T1	19		T2	27		T4	11
valid_sources[0x6e]	137138	1			T1	12		T2	20		T3	10
valid_sources[0x6f]	153184	1			T1	8		T2	43		T3	5
valid_sources[0x70]	134368	1			T1	6		T2	33		T3	11
valid_sources[0x71]	136493	1			T1	9		T2	40		T3	5
valid_sources[0x72]	142872	1			T1	7		T2	9		T3	3
valid_sources[0x73]	135195	1			T1	2		T2	23		T3	7
valid_sources[0x74]	134018	1			T1	14		T2	50		T4	6
valid_sources[0x75]	133366	1			T1	6		T2	34		T3	6
valid_sources[0x76]	149420	1			T1	5		T2	51		T3	4
valid_sources[0x77]	147687	1			T1	11		T2	48		T3	13
valid_sources[0x78]	146812	1			T1	14		T2	11		T3	3
valid_sources[0x79]	133414	1			T1	11		T2	11		T3	3
valid_sources[0x7a]	146592	1			T1	9		T2	28		T3	1
valid_sources[0x7b]	147389	1			T1	6		T2	48		T3	6
valid_sources[0x7c]	150379	1			T1	15		T2	24		T3	5
valid_sources[0x7d]	166922	1			T1	9		T2	31		T3	5
valid_sources[0x7e]	160784	1			T1	9		T2	8		T3	3
valid_sources[0x7f]	150783	1			T1	9		T2	23		T3	6
valid_sources[0x80]	138642	1			T1	6		T2	40		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7182193

1

T1

977

T2

1238

T3

211

values[0x0]

all_enables

biggest_size

219869

1

T1

31

T2

529

T3

99

values[0x1]

all_enables

biggest_size

151910

1

T1

18

T2

293

T3

78