Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	409589343	0	0	0
ctrl_rd_A	409589343	2173	0	0
host_fifo_config_rd_A	409589343	6024	0	0
host_nack_handler_timeout_rd_A	409589343	1339	0	0
host_timeout_ctrl_rd_A	409589343	1144	0	0
intr_enable_rd_A	409589343	3451	0	0
ovrd_rd_A	409589343	2331	0	0
target_fifo_config_rd_A	409589343	1412	0	0
target_id_rd_A	409589343	1532	0	0
target_timeout_ctrl_rd_A	409589343	1164	0	0
timeout_ctrl_rd_A	409589343	1606	0	0
timing0_rd_A	409589343	1294	0	0
timing1_rd_A	409589343	1526	0	0
timing2_rd_A	409589343	1414	0	0
timing3_rd_A	409589343	1483	0	0
timing4_rd_A	409589343	1331	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	2173	0	0
T97	12374	187	0	0
T98	2732	44	0	0
T99	27105	256	0	0
T100	6639	24	0	0
T101	6432	116	0	0
T102	2849	19	0	0
T103	5746	8	0	0
T104	6798	22	0	0
T105	2687	7	0	0
T106	1910	16	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	6024	0	0
T32	536893	175	0	0
T37	0	186	0	0
T47	12992	0	0	0
T54	10547	0	0	0
T75	484110	81	0	0
T93	6186	0	0	0
T107	0	167	0	0
T108	0	117	0	0
T109	0	56	0	0
T110	0	257	0	0
T111	0	123	0	0
T112	0	102	0	0
T113	0	161	0	0
T114	151909	0	0	0
T115	31823	0	0	0
T116	158080	0	0	0
T117	45447	0	0	0
T118	415404	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1339	0	0
T97	12374	79	0	0
T98	2732	25	0	0
T99	27105	230	0	0
T100	6639	4	0	0
T101	6432	44	0	0
T102	2849	11	0	0
T103	5746	20	0	0
T104	6798	15	0	0
T105	2687	19	0	0
T119	10482	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1144	0	0
T97	12374	29	0	0
T98	2732	19	0	0
T99	27105	214	0	0
T100	6639	11	0	0
T101	6432	25	0	0
T102	2849	14	0	0
T103	5746	11	0	0
T104	6798	28	0	0
T105	2687	5	0	0
T119	10482	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	3451	0	0
T34	199572	44	0	0
T97	0	277	0	0
T98	0	49	0	0
T99	0	232	0	0
T100	0	57	0	0
T101	0	81	0	0
T102	0	5	0	0
T119	0	27	0	0
T120	0	9	0	0
T121	0	21	0	0
T122	39275	0	0	0
T123	128328	0	0	0
T124	106114	0	0	0
T125	99510	0	0	0
T126	132289	0	0	0
T127	80911	0	0	0
T128	502460	0	0	0
T129	65719	0	0	0
T130	6987	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	2331	0	0
T32	536893	0	0	0
T47	12992	0	0	0
T75	484110	0	0	0
T91	1296	75	0	0
T92	10747	0	0	0
T93	6186	0	0	0
T114	151909	0	0	0
T115	31823	0	0	0
T116	158080	0	0	0
T117	45447	0	0	0
T131	0	46	0	0
T132	0	44	0	0
T133	0	41	0	0
T134	0	82	0	0
T135	0	41	0	0
T136	0	65	0	0
T137	0	72	0	0
T138	0	38	0	0
T139	0	24	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1412	0	0
T97	12374	68	0	0
T98	2732	49	0	0
T99	27105	250	0	0
T100	6639	23	0	0
T101	6432	40	0	0
T102	2849	16	0	0
T103	5746	9	0	0
T104	6798	12	0	0
T105	2687	17	0	0
T119	10482	17	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1532	0	0
T97	12374	77	0	0
T98	2732	24	0	0
T99	27105	197	0	0
T100	6639	73	0	0
T101	6432	47	0	0
T102	2849	7	0	0
T103	5746	10	0	0
T104	6798	20	0	0
T105	2687	28	0	0
T119	10482	3	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1164	0	0
T97	12374	55	0	0
T99	27105	203	0	0
T100	6639	47	0	0
T101	6432	20	0	0
T102	2849	1	0	0
T103	5746	4	0	0
T104	6798	11	0	0
T105	2687	3	0	0
T106	1910	9	0	0
T119	10482	12	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1606	0	0
T97	12374	109	0	0
T98	2732	30	0	0
T99	27105	206	0	0
T100	6639	34	0	0
T101	6432	35	0	0
T102	2849	10	0	0
T103	5746	14	0	0
T104	6798	17	0	0
T105	2687	23	0	0
T119	10482	15	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1294	0	0
T97	12374	55	0	0
T98	2732	24	0	0
T99	27105	238	0	0
T100	6639	49	0	0
T101	6432	25	0	0
T102	2849	14	0	0
T103	5746	9	0	0
T104	6798	35	0	0
T105	2687	17	0	0
T119	10482	2	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1526	0	0
T97	12374	75	0	0
T98	2732	16	0	0
T99	27105	216	0	0
T100	6639	61	0	0
T101	6432	26	0	0
T102	2849	12	0	0
T103	5746	3	0	0
T104	6798	9	0	0
T105	2687	10	0	0
T140	23407	136	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1414	0	0
T97	12374	79	0	0
T98	2732	6	0	0
T99	27105	244	0	0
T100	6639	43	0	0
T101	6432	17	0	0
T102	2849	29	0	0
T103	5746	20	0	0
T104	6798	17	0	0
T105	2687	10	0	0
T106	1910	1	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1483	0	0
T97	12374	56	0	0
T98	2732	29	0	0
T99	27105	224	0	0
T100	6639	50	0	0
T101	6432	30	0	0
T102	2849	10	0	0
T103	5746	8	0	0
T104	6798	27	0	0
T105	2687	7	0	0
T119	10482	21	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409589343	1331	0	0
T97	12374	34	0	0
T98	2732	14	0	0
T99	27105	213	0	0
T100	6639	20	0	0
T101	6432	18	0	0
T102	2849	12	0	0
T103	5746	7	0	0
T104	6798	23	0	0
T105	2687	3	0	0
T119	10482	15	0	0