Group : i2c_env_pkg::i2c_scl_sda_override_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_scl_sda_override_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.scl_sda_override_cg 100.00 1 100 1 64 64



Group Instance : i2c_env_pkg.scl_sda_override_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance i2c_env_pkg.scl_sda_override_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_sclval 2 0 2 100.00 100 1 1 2
cp_sdaval 2 0 2 100.00 100 1 1 2
cp_txorvden 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cp_txorvden_x_sclval 4 0 4 100.00 100 1 1 0
cp_txorvden_x_sdaval 4 0 4 100.00 100 1 1 0


Summary for Variable cp_sclval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sclval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 373 1 T7 13 T49 7 T69 6
auto[1] 390 1 T7 7 T49 6 T69 13


Summary for Variable cp_sdaval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sdaval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 391 1 T7 9 T49 7 T69 10
auto[1] 372 1 T7 11 T49 6 T69 9


Summary for Variable cp_txorvden

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txorvden

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 359 1 T7 9 T49 9 T69 12
auto[1] 404 1 T7 11 T49 4 T69 7


Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins
cp_txorvden   cp_sclval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 171 1 T7 5 T49 4 T69 2
auto[0] auto[1] 188 1 T7 4 T49 5 T69 10
auto[1] auto[0] 202 1 T7 8 T49 3 T69 4
auto[1] auto[1] 202 1 T7 3 T49 1 T69 3


Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins
cp_txorvden   cp_sdaval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 184 1 T7 4 T49 5 T69 7
auto[0] auto[1] 175 1 T7 5 T49 4 T69 5
auto[1] auto[0] 207 1 T7 5 T49 2 T69 3
auto[1] auto[1] 197 1 T7 6 T49 2 T69 4