Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32011681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8716978

1

T1

21

T2

569

T3

168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39884923	1			T1	4		T2	1804		T3	4439
values[0x0]	421129	1			T1	15		T2	84		T3	95
values[0x1]	422607	1			T1	28		T2	79		T3	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22438230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18290429

1

T1

27

T2

958

T3

2342

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	172380	1			T2	6		T3	11		T64	2
valid_sources[0x01]	191239	1			T2	4		T3	24		T5	3
valid_sources[0x02]	154756	1			T2	4		T3	11		T5	1
valid_sources[0x03]	145453	1			T2	10		T3	10		T54	1
valid_sources[0x04]	151210	1			T1	1		T2	4		T3	21
valid_sources[0x05]	165849	1			T2	9		T3	18		T5	1
valid_sources[0x06]	161074	1			T2	10		T3	14		T54	2
valid_sources[0x07]	149609	1			T2	13		T3	33		T10	1
valid_sources[0x08]	163042	1			T2	7		T3	8		T54	2
valid_sources[0x09]	144366	1			T2	10		T3	41		T9	1
valid_sources[0x0a]	151258	1			T2	4		T3	20		T5	1
valid_sources[0x0b]	165092	1			T2	16		T14	23		T11	7
valid_sources[0x0c]	160845	1			T2	4		T3	24		T54	1
valid_sources[0x0d]	172585	1			T1	1		T2	5		T3	8
valid_sources[0x0e]	168716	1			T2	3		T3	6		T7	1
valid_sources[0x0f]	153310	1			T2	12		T3	8		T54	5
valid_sources[0x10]	153508	1			T2	6		T3	8		T9	1
valid_sources[0x11]	161268	1			T2	5		T3	7		T5	1
valid_sources[0x12]	166336	1			T2	10		T3	23		T5	1
valid_sources[0x13]	150208	1			T2	12		T3	15		T5	2
valid_sources[0x14]	156352	1			T2	7		T3	10		T9	2
valid_sources[0x15]	163058	1			T1	1		T2	10		T3	19
valid_sources[0x16]	151149	1			T2	11		T3	12		T9	2
valid_sources[0x17]	182993	1			T1	1		T2	8		T3	1
valid_sources[0x18]	156851	1			T2	7		T3	11		T64	3
valid_sources[0x19]	151331	1			T2	7		T3	1		T54	1
valid_sources[0x1a]	156567	1			T2	12		T3	28		T7	1
valid_sources[0x1b]	206833	1			T2	4		T3	8		T5	1
valid_sources[0x1c]	158423	1			T2	8		T54	2		T14	22
valid_sources[0x1d]	154105	1			T2	18		T3	20		T54	1
valid_sources[0x1e]	145330	1			T2	4		T3	4		T9	2
valid_sources[0x1f]	168046	1			T1	1		T2	7		T3	12
valid_sources[0x20]	159997	1			T1	1		T2	5		T3	44
valid_sources[0x21]	156109	1			T2	8		T3	34		T5	1
valid_sources[0x22]	152491	1			T2	7		T3	8		T14	32
valid_sources[0x23]	147980	1			T2	11		T14	37		T11	5
valid_sources[0x24]	164261	1			T2	10		T3	36		T9	1
valid_sources[0x25]	163571	1			T2	5		T3	16		T54	3
valid_sources[0x26]	157143	1			T2	3		T3	38		T10	2
valid_sources[0x27]	151074	1			T2	9		T64	1		T14	23
valid_sources[0x28]	146758	1			T2	15		T3	14		T5	1
valid_sources[0x29]	156183	1			T2	7		T3	25		T5	1
valid_sources[0x2a]	155345	1			T2	21		T3	20		T5	2
valid_sources[0x2b]	154649	1			T2	7		T3	2		T5	1
valid_sources[0x2c]	163889	1			T2	1		T3	37		T54	1
valid_sources[0x2d]	155209	1			T2	4		T3	20		T7	2
valid_sources[0x2e]	187566	1			T2	6		T3	13		T64	2
valid_sources[0x2f]	153788	1			T2	7		T3	14		T9	1
valid_sources[0x30]	162652	1			T2	7		T3	14		T5	2
valid_sources[0x31]	159919	1			T2	3		T3	6		T9	1
valid_sources[0x32]	153187	1			T2	3		T3	3		T54	2
valid_sources[0x33]	145052	1			T2	7		T3	1		T5	1
valid_sources[0x34]	169528	1			T2	3		T3	16		T9	1
valid_sources[0x35]	158312	1			T1	2		T2	8		T3	69
valid_sources[0x36]	153191	1			T2	1		T3	56		T64	2
valid_sources[0x37]	151387	1			T2	3		T3	5		T54	4
valid_sources[0x38]	148133	1			T2	9		T3	20		T54	1
valid_sources[0x39]	164558	1			T2	15		T3	4		T54	2
valid_sources[0x3a]	153682	1			T2	7		T3	3		T5	3
valid_sources[0x3b]	155345	1			T1	1		T2	9		T3	33
valid_sources[0x3c]	177425	1			T2	3		T3	1		T54	1
valid_sources[0x3d]	155143	1			T2	12		T3	13		T64	2
valid_sources[0x3e]	158638	1			T1	1		T2	9		T3	19
valid_sources[0x3f]	155637	1			T2	13		T3	12		T5	1
valid_sources[0x40]	164173	1			T2	14		T3	3		T10	1
valid_sources[0x41]	148840	1			T2	8		T3	49		T5	2
valid_sources[0x42]	153894	1			T2	9		T3	105		T64	2
valid_sources[0x43]	153562	1			T2	12		T3	48		T9	1
valid_sources[0x44]	156160	1			T1	3		T2	5		T3	34
valid_sources[0x45]	158059	1			T2	3		T3	9		T5	1
valid_sources[0x46]	155246	1			T2	6		T9	1		T64	2
valid_sources[0x47]	157946	1			T2	7		T3	4		T5	1
valid_sources[0x48]	175892	1			T2	15		T3	20		T5	1
valid_sources[0x49]	163152	1			T2	8		T54	1		T64	1
valid_sources[0x4a]	160333	1			T2	6		T10	4		T54	3
valid_sources[0x4b]	153759	1			T2	6		T3	59		T64	1
valid_sources[0x4c]	149279	1			T2	12		T3	6		T5	1
valid_sources[0x4d]	152119	1			T2	5		T3	20		T5	4
valid_sources[0x4e]	153116	1			T2	10		T10	1		T54	1
valid_sources[0x4f]	175438	1			T1	1		T2	8		T3	7
valid_sources[0x50]	159884	1			T2	5		T3	2		T5	2
valid_sources[0x51]	167497	1			T2	5		T3	22		T5	1
valid_sources[0x52]	147153	1			T2	4		T14	25		T11	11
valid_sources[0x53]	146290	1			T2	8		T3	33		T10	1
valid_sources[0x54]	160288	1			T2	10		T3	15		T5	1
valid_sources[0x55]	153600	1			T1	1		T2	7		T3	6
valid_sources[0x56]	160926	1			T2	6		T3	51		T5	1
valid_sources[0x57]	173913	1			T2	10		T3	20		T5	2
valid_sources[0x58]	168268	1			T2	5		T3	30		T9	3
valid_sources[0x59]	161599	1			T1	2		T2	10		T3	15
valid_sources[0x5a]	147406	1			T2	11		T3	19		T54	4
valid_sources[0x5b]	157497	1			T2	8		T3	18		T54	4
valid_sources[0x5c]	153580	1			T2	6		T3	7		T9	1
valid_sources[0x5d]	155462	1			T1	1		T2	4		T3	4
valid_sources[0x5e]	152534	1			T2	11		T3	47		T9	1
valid_sources[0x5f]	169395	1			T2	6		T3	2		T9	4
valid_sources[0x60]	157368	1			T2	10		T3	11		T5	3
valid_sources[0x61]	147726	1			T2	9		T3	8		T9	3
valid_sources[0x62]	161078	1			T2	5		T3	7		T54	2
valid_sources[0x63]	168375	1			T2	7		T3	23		T5	1
valid_sources[0x64]	158843	1			T2	4		T3	6		T10	5
valid_sources[0x65]	154704	1			T2	16		T3	11		T5	3
valid_sources[0x66]	161708	1			T2	7		T5	1		T54	3
valid_sources[0x67]	161808	1			T2	6		T3	28		T5	3
valid_sources[0x68]	150164	1			T2	9		T3	20		T7	1
valid_sources[0x69]	168683	1			T2	7		T3	7		T64	1
valid_sources[0x6a]	157038	1			T2	12		T3	17		T5	1
valid_sources[0x6b]	144270	1			T1	2		T2	6		T54	2
valid_sources[0x6c]	165932	1			T2	9		T3	16		T9	1
valid_sources[0x6d]	153422	1			T2	12		T3	19		T5	1
valid_sources[0x6e]	151592	1			T2	7		T3	9		T5	1
valid_sources[0x6f]	152435	1			T2	8		T3	47		T5	1
valid_sources[0x70]	152076	1			T2	14		T3	6		T5	1
valid_sources[0x71]	147578	1			T1	1		T2	8		T3	12
valid_sources[0x72]	152695	1			T2	7		T3	23		T64	1
valid_sources[0x73]	152185	1			T2	5		T3	23		T5	1
valid_sources[0x74]	157184	1			T2	2		T3	10		T5	3
valid_sources[0x75]	163353	1			T2	10		T3	28		T14	35
valid_sources[0x76]	144734	1			T1	3		T2	6		T3	28
valid_sources[0x77]	164969	1			T1	1		T2	3		T3	25
valid_sources[0x78]	170427	1			T2	7		T3	4		T54	3
valid_sources[0x79]	159493	1			T2	17		T3	11		T14	35
valid_sources[0x7a]	150352	1			T2	12		T3	17		T4	1061
valid_sources[0x7b]	145425	1			T2	8		T3	26		T5	3
valid_sources[0x7c]	156268	1			T1	2		T2	5		T3	66
valid_sources[0x7d]	164693	1			T2	8		T3	10		T5	1
valid_sources[0x7e]	160665	1			T2	6		T3	32		T64	2
valid_sources[0x7f]	147540	1			T2	5		T3	22		T9	1
valid_sources[0x80]	171683	1			T2	7		T3	65		T54	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8343262

1

T1

1

T2

435

T3

96

values[0x0]

all_enables

biggest_size

221673

1

T1

6

T2

71

T3

49

values[0x1]

all_enables

biggest_size

152043

1

T1

14

T2

63

T3

23