Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_target_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	2082	1			T15	4		T31	2		T32	5
b2b_read_same_addr	336	1			T21	2		T22	4		T17	1
write_after_read_different_addr	2076	1			T15	11		T31	6		T32	11
write_after_read_same_addr	35	1			T41	1		T44	1		T38	1
read_after_write_different_addr	2087	1			T15	11		T31	7		T32	11
read_after_write_same_addr	30	1			T282	1		T86	1		T98	1
b2b_write_different_addr	2159	1			T15	13		T31	12		T32	11
b2b_write_same_addr	361	1			T41	1		T16	1		T283	2

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	5346	1			T2	28		T4	34		T10	14
b2b_read_same_addr	12641	1			T1	3		T2	25		T3	9
write_after_read_different_addr	5174	1			T1	5		T3	8		T4	47
write_after_read_same_addr	108	1			T284	9		T56	1		T285	19
read_after_write_different_addr	5184	1			T1	6		T3	9		T4	48
read_after_write_same_addr	99	1			T284	7		T285	19		T286	1
b2b_write_different_addr	5173	1			T6	21		T8	5		T9	1
b2b_write_same_addr	12060	1			T1	10		T3	16		T4	32