Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413457620	0	0	0
ctrl_rd_A	413457620	3636	0	0
host_fifo_config_rd_A	413457620	6208	0	0
host_nack_handler_timeout_rd_A	413457620	2161	0	0
host_timeout_ctrl_rd_A	413457620	1995	0	0
intr_enable_rd_A	413457620	6302	0	0
ovrd_rd_A	413457620	3298	0	0
target_fifo_config_rd_A	413457620	2343	0	0
target_id_rd_A	413457620	2775	0	0
target_timeout_ctrl_rd_A	413457620	2277	0	0
timeout_ctrl_rd_A	413457620	2531	0	0
timing0_rd_A	413457620	2255	0	0
timing1_rd_A	413457620	2353	0	0
timing2_rd_A	413457620	2141	0	0
timing3_rd_A	413457620	2317	0	0
timing4_rd_A	413457620	2439	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	3636	0	0
T88	5448	28	0	0
T89	10662	234	0	0
T90	22729	139	0	0
T91	1220	1	0	0
T92	2425	22	0	0
T93	3783	2	0	0
T94	2026	11	0	0
T95	4641	14	0	0
T96	3724	2	0	0
T97	51726	411	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	6208	0	0
T18	0	135	0	0
T20	13666	0	0	0
T38	431566	0	0	0
T71	468232	81	0	0
T87	251336	0	0	0
T98	0	235	0	0
T99	0	72	0	0
T100	0	123	0	0
T101	0	338	0	0
T102	0	148	0	0
T103	0	124	0	0
T104	0	112	0	0
T105	0	238	0	0
T106	11584	0	0	0
T107	888	0	0	0
T108	11678	0	0	0
T109	129814	0	0	0
T110	107334	0	0	0
T111	53182	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2161	0	0
T88	5448	24	0	0
T89	10662	251	0	0
T90	22729	141	0	0
T91	1220	1	0	0
T92	2425	11	0	0
T93	3783	25	0	0
T94	2026	9	0	0
T96	3724	14	0	0
T97	51726	471	0	0
T112	2141	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	1995	0	0
T88	5448	65	0	0
T89	10662	211	0	0
T90	22729	127	0	0
T91	1220	1	0	0
T92	2425	3	0	0
T93	3783	16	0	0
T94	2026	7	0	0
T95	4641	11	0	0
T96	3724	19	0	0
T97	51726	366	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	6302	0	0
T18	100219	30	0	0
T88	0	21	0	0
T89	0	276	0	0
T90	0	147	0	0
T91	0	2	0	0
T92	0	8	0	0
T101	0	17	0	0
T113	0	6	0	0
T114	0	23	0	0
T115	0	24	0	0
T116	12691	0	0	0
T117	57175	0	0	0
T118	94966	0	0	0
T119	91037	0	0	0
T120	115762	0	0	0
T121	14507	0	0	0
T122	17124	0	0	0
T123	10210	0	0	0
T124	18531	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	3298	0	0
T19	8084	0	0	0
T43	11489	0	0	0
T44	87469	0	0	0
T55	596630	0	0	0
T58	54551	0	0	0
T62	41348	0	0	0
T63	52809	0	0	0
T69	3065	65	0	0
T125	0	64	0	0
T126	0	60	0	0
T127	0	48	0	0
T128	0	48	0	0
T129	0	38	0	0
T130	0	64	0	0
T131	0	15	0	0
T132	0	32	0	0
T133	0	33	0	0
T134	154094	0	0	0
T135	79202	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2343	0	0
T88	5448	29	0	0
T89	10662	206	0	0
T90	22729	157	0	0
T92	2425	8	0	0
T93	3783	6	0	0
T94	2026	14	0	0
T95	4641	26	0	0
T96	3724	28	0	0
T97	51726	419	0	0
T112	2141	21	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2775	0	0
T88	5448	48	0	0
T89	10662	236	0	0
T90	22729	127	0	0
T91	1220	5	0	0
T92	2425	19	0	0
T93	3783	12	0	0
T94	2026	9	0	0
T95	4641	19	0	0
T96	3724	12	0	0
T97	51726	467	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2277	0	0
T88	5448	30	0	0
T89	10662	223	0	0
T90	22729	140	0	0
T91	1220	2	0	0
T92	2425	4	0	0
T93	3783	21	0	0
T94	2026	2	0	0
T95	4641	18	0	0
T96	3724	26	0	0
T97	51726	434	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2531	0	0
T88	5448	33	0	0
T89	10662	246	0	0
T90	22729	178	0	0
T92	2425	23	0	0
T93	3783	17	0	0
T94	2026	4	0	0
T95	4641	59	0	0
T96	3724	7	0	0
T97	51726	443	0	0
T112	2141	13	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2255	0	0
T88	5448	44	0	0
T89	10662	201	0	0
T90	22729	113	0	0
T91	1220	8	0	0
T92	2425	19	0	0
T93	3783	48	0	0
T94	2026	3	0	0
T95	4641	22	0	0
T96	3724	10	0	0
T97	51726	469	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2353	0	0
T88	5448	33	0	0
T89	10662	239	0	0
T90	22729	124	0	0
T91	1220	9	0	0
T92	2425	12	0	0
T93	3783	31	0	0
T94	2026	15	0	0
T95	4641	26	0	0
T96	3724	2	0	0
T97	51726	491	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2141	0	0
T88	5448	35	0	0
T89	10662	243	0	0
T90	22729	122	0	0
T92	2425	6	0	0
T93	3783	28	0	0
T94	2026	9	0	0
T95	4641	22	0	0
T96	3724	18	0	0
T97	51726	437	0	0
T112	2141	1	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2317	0	0
T88	5448	30	0	0
T89	10662	198	0	0
T90	22729	138	0	0
T91	1220	1	0	0
T92	2425	20	0	0
T93	3783	19	0	0
T94	2026	5	0	0
T95	4641	21	0	0
T96	3724	25	0	0
T97	51726	431	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413457620	2439	0	0
T88	5448	96	0	0
T89	10662	241	0	0
T90	22729	126	0	0
T91	1220	6	0	0
T92	2425	4	0	0
T93	3783	30	0	0
T94	2026	13	0	0
T95	4641	26	0	0
T96	3724	61	0	0
T97	51726	465	0	0