Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

43445

1

T1

18

T2

429

T3

638

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34731	1			T1	20		T2	156		T3	167
values[0x0]	16687	1			T1	11		T2	159		T3	232
values[0x1]	17665	1			T1	9		T2	170		T3	299

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17885	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51198

1

T1

23

T2

454

T3

675

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	302	1			T1	1		T3	2		T4	2
valid_sources[0x01]	251	1			T3	2		T4	1		T9	6
valid_sources[0x02]	411	1			T3	4		T7	1		T4	1
valid_sources[0x03]	229	1			T3	4		T4	5		T9	3
valid_sources[0x04]	279	1			T3	1		T4	1		T9	5
valid_sources[0x05]	335	1			T3	1		T8	10		T4	3
valid_sources[0x06]	344	1			T3	3		T4	5		T9	4
valid_sources[0x07]	325	1			T3	2		T4	1		T9	3
valid_sources[0x08]	236	1			T3	1		T4	1		T9	7
valid_sources[0x09]	238	1			T3	4		T4	2		T9	1
valid_sources[0x0a]	222	1			T3	2		T4	1		T9	2
valid_sources[0x0b]	310	1			T4	5		T9	8		T5	2
valid_sources[0x0c]	476	1			T3	2		T4	2		T9	4
valid_sources[0x0d]	216	1			T3	4		T8	10		T9	7
valid_sources[0x0e]	250	1			T3	2		T4	3		T9	6
valid_sources[0x0f]	197	1			T3	8		T4	3		T9	4
valid_sources[0x10]	297	1			T1	2		T3	2		T8	10
valid_sources[0x11]	226	1			T1	1		T3	4		T9	6
valid_sources[0x12]	261	1			T3	2		T8	36		T4	4
valid_sources[0x13]	259	1			T4	1		T9	4		T5	2
valid_sources[0x14]	266	1			T3	3		T4	4		T9	3
valid_sources[0x15]	267	1			T4	5		T9	3		T5	2
valid_sources[0x16]	256	1			T3	3		T8	25		T4	2
valid_sources[0x17]	282	1			T4	1		T9	7		T5	3
valid_sources[0x18]	228	1			T3	2		T4	4		T9	5
valid_sources[0x19]	689	1			T3	6		T4	2		T9	4
valid_sources[0x1a]	234	1			T3	6		T9	6		T22	4
valid_sources[0x1b]	293	1			T4	5		T9	10		T12	1
valid_sources[0x1c]	289	1			T4	1		T9	13		T5	5
valid_sources[0x1d]	313	1			T3	3		T7	2		T8	10
valid_sources[0x1e]	220	1			T1	1		T3	1		T4	3
valid_sources[0x1f]	268	1			T3	2		T4	5		T9	2
valid_sources[0x20]	241	1			T3	2		T4	2		T9	3
valid_sources[0x21]	207	1			T3	1		T4	5		T9	4
valid_sources[0x22]	201	1			T3	5		T4	3		T9	8
valid_sources[0x23]	263	1			T3	3		T7	1		T4	2
valid_sources[0x24]	252	1			T3	2		T4	5		T9	6
valid_sources[0x25]	254	1			T3	2		T8	10		T4	1
valid_sources[0x26]	232	1			T3	3		T4	3		T9	9
valid_sources[0x27]	240	1			T3	1		T4	2		T9	5
valid_sources[0x28]	242	1			T3	2		T4	1		T9	1
valid_sources[0x29]	177	1			T1	1		T3	6		T4	1
valid_sources[0x2a]	270	1			T3	2		T7	1		T4	3
valid_sources[0x2b]	292	1			T3	7		T4	2		T9	3
valid_sources[0x2c]	287	1			T3	4		T4	2		T9	4
valid_sources[0x2d]	275	1			T3	2		T4	4		T5	2
valid_sources[0x2e]	192	1			T4	2		T9	8		T5	2
valid_sources[0x2f]	283	1			T3	8		T4	1		T9	4
valid_sources[0x30]	211	1			T3	4		T4	4		T9	3
valid_sources[0x31]	194	1			T3	7		T7	1		T4	1
valid_sources[0x32]	227	1			T3	1		T9	10		T5	1
valid_sources[0x33]	203	1			T9	1		T5	2		T22	4
valid_sources[0x34]	304	1			T3	2		T7	1		T9	6
valid_sources[0x35]	225	1			T3	3		T9	2		T5	4
valid_sources[0x36]	256	1			T3	1		T4	2		T9	1
valid_sources[0x37]	246	1			T4	1		T9	3		T14	2
valid_sources[0x38]	195	1			T3	1		T4	4		T9	8
valid_sources[0x39]	526	1			T2	230		T3	2		T7	1
valid_sources[0x3a]	584	1			T3	2		T8	10		T9	10
valid_sources[0x3b]	278	1			T3	4		T4	5		T9	2
valid_sources[0x3c]	257	1			T3	1		T4	2		T9	4
valid_sources[0x3d]	313	1			T7	2		T4	1		T9	6
valid_sources[0x3e]	287	1			T4	2		T9	14		T5	5
valid_sources[0x3f]	281	1			T1	3		T3	5		T4	1
valid_sources[0x40]	249	1			T1	1		T9	6		T5	4
valid_sources[0x41]	292	1			T1	2		T3	3		T7	1
valid_sources[0x42]	201	1			T4	2		T9	7		T5	1
valid_sources[0x43]	346	1			T4	1		T9	5		T6	2
valid_sources[0x44]	271	1			T8	10		T4	2		T9	5
valid_sources[0x45]	252	1			T3	6		T4	1		T9	6
valid_sources[0x46]	213	1			T1	1		T3	4		T4	2
valid_sources[0x47]	239	1			T3	1		T7	1		T4	3
valid_sources[0x48]	209	1			T3	3		T8	2		T4	2
valid_sources[0x49]	282	1			T3	5		T7	2		T8	10
valid_sources[0x4a]	227	1			T3	2		T4	1		T9	4
valid_sources[0x4b]	215	1			T3	4		T4	2		T9	4
valid_sources[0x4c]	218	1			T3	7		T4	3		T9	7
valid_sources[0x4d]	251	1			T3	2		T4	2		T9	5
valid_sources[0x4e]	248	1			T3	5		T9	1		T5	6
valid_sources[0x4f]	183	1			T3	2		T4	2		T9	3
valid_sources[0x50]	216	1			T3	3		T4	1		T9	5
valid_sources[0x51]	226	1			T1	1		T8	10		T4	3
valid_sources[0x52]	252	1			T3	3		T4	2		T9	1
valid_sources[0x53]	273	1			T3	4		T4	2		T9	10
valid_sources[0x54]	337	1			T3	6		T4	3		T9	5
valid_sources[0x55]	222	1			T9	2		T5	4		T6	1
valid_sources[0x56]	242	1			T1	1		T4	6		T9	11
valid_sources[0x57]	266	1			T3	1		T4	5		T9	6
valid_sources[0x58]	248	1			T3	3		T4	3		T9	6
valid_sources[0x59]	260	1			T3	7		T8	10		T4	1
valid_sources[0x5a]	326	1			T3	4		T8	10		T4	1
valid_sources[0x5b]	366	1			T3	5		T8	10		T4	2
valid_sources[0x5c]	257	1			T3	3		T9	4		T5	4
valid_sources[0x5d]	241	1			T3	1		T4	6		T5	3
valid_sources[0x5e]	325	1			T3	3		T4	1		T9	4
valid_sources[0x5f]	376	1			T3	1		T4	2		T9	4
valid_sources[0x60]	223	1			T3	9		T4	2		T9	9
valid_sources[0x61]	272	1			T3	2		T4	2		T5	1
valid_sources[0x62]	234	1			T4	1		T5	2		T13	8
valid_sources[0x63]	259	1			T4	1		T9	7		T5	4
valid_sources[0x64]	294	1			T1	1		T3	4		T8	31
valid_sources[0x65]	246	1			T3	3		T9	3		T5	2
valid_sources[0x66]	216	1			T3	2		T4	1		T9	3
valid_sources[0x67]	211	1			T1	1		T3	4		T4	1
valid_sources[0x68]	286	1			T3	1		T4	2		T9	7
valid_sources[0x69]	317	1			T3	4		T4	1		T9	13
valid_sources[0x6a]	224	1			T3	2		T4	3		T9	7
valid_sources[0x6b]	288	1			T3	5		T4	2		T9	6
valid_sources[0x6c]	243	1			T3	3		T8	1		T4	3
valid_sources[0x6d]	169	1			T4	3		T9	10		T5	1
valid_sources[0x6e]	212	1			T1	1		T3	3		T4	4
valid_sources[0x6f]	241	1			T3	1		T8	2		T4	2
valid_sources[0x70]	198	1			T3	1		T4	1		T9	4
valid_sources[0x71]	301	1			T3	4		T8	9		T4	1
valid_sources[0x72]	279	1			T3	3		T4	4		T9	4
valid_sources[0x73]	278	1			T3	1		T4	1		T9	4
valid_sources[0x74]	260	1			T3	3		T4	4		T9	9
valid_sources[0x75]	299	1			T3	5		T4	3		T9	5
valid_sources[0x76]	194	1			T3	2		T4	4		T9	2
valid_sources[0x77]	194	1			T1	1		T3	3		T4	2
valid_sources[0x78]	235	1			T3	6		T4	1		T9	3
valid_sources[0x79]	286	1			T3	6		T4	2		T9	1
valid_sources[0x7a]	239	1			T3	1		T4	1		T9	9
valid_sources[0x7b]	257	1			T3	3		T4	2		T9	19
valid_sources[0x7c]	298	1			T4	3		T9	3		T5	3
valid_sources[0x7d]	282	1			T3	8		T4	2		T9	3
valid_sources[0x7e]	307	1			T3	8		T4	2		T9	4
valid_sources[0x7f]	505	1			T4	3		T9	1		T5	2
valid_sources[0x80]	370	1			T3	3		T9	6		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15794

1

T1

11

T2

112

T3

166

values[0x0]

all_enables

biggest_size

14223

1

T1

4

T2

155

T3

231

values[0x1]

all_enables

biggest_size

13428

1

T1

3

T2

162

T3

241