Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	652987	0	0	0
ctrl_rd_A	652987	2680	0	0
host_fifo_config_rd_A	652987	1796	0	0
host_nack_handler_timeout_rd_A	652987	1707	0	0
host_timeout_ctrl_rd_A	652987	1512	0	0
intr_enable_rd_A	652987	4010	0	0
ovrd_rd_A	652987	1923	0	0
target_fifo_config_rd_A	652987	1697	0	0
target_id_rd_A	652987	2183	0	0
target_timeout_ctrl_rd_A	652987	1723	0	0
timeout_ctrl_rd_A	652987	1969	0	0
timing0_rd_A	652987	1664	0	0
timing1_rd_A	652987	1708	0	0
timing2_rd_A	652987	1650	0	0
timing3_rd_A	652987	1638	0	0
timing4_rd_A	652987	1835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	2680	0	0
T4	4701	36	0	0
T5	5293	0	0	0
T6	1488	33	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	42	0	0
T18	0	43	0	0
T21	1740	0	0	0
T28	0	12	0	0
T32	0	41	0	0
T45	0	142	0	0
T46	0	15	0	0
T47	0	353	0	0
T48	0	12	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1796	0	0
T4	4701	20	0	0
T5	5293	0	0	0
T6	1488	6	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	4	0	0
T18	0	14	0	0
T21	1740	0	0	0
T28	0	10	0	0
T32	0	12	0	0
T45	0	62	0	0
T46	0	36	0	0
T47	0	140	0	0
T48	0	9	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1707	0	0
T4	4701	18	0	0
T5	5293	0	0	0
T6	1488	0	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	5	0	0
T18	0	15	0	0
T21	1740	0	0	0
T28	0	10	0	0
T32	0	10	0	0
T45	0	50	0	0
T46	0	15	0	0
T47	0	123	0	0
T48	0	25	0	0
T49	0	29	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1512	0	0
T4	4701	12	0	0
T5	5293	0	0	0
T6	1488	6	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	11	0	0
T18	0	22	0	0
T21	1740	0	0	0
T28	0	6	0	0
T32	0	7	0	0
T45	0	26	0	0
T46	0	18	0	0
T47	0	70	0	0
T48	0	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	4010	0	0
T4	4701	0	0	0
T5	5293	0	0	0
T6	1488	0	0	0
T7	1448	17	0	0
T8	5364	0	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T17	0	17	0	0
T18	0	16	0	0
T21	0	1	0	0
T28	0	56	0	0
T45	0	342	0	0
T46	0	30	0	0
T47	0	430	0	0
T50	0	27	0	0
T51	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1923	0	0
T4	4701	6	0	0
T5	5293	0	0	0
T6	1488	4	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	14	0	0
T18	0	26	0	0
T21	1740	0	0	0
T28	0	6	0	0
T32	0	13	0	0
T45	0	57	0	0
T46	0	5	0	0
T47	0	128	0	0
T48	0	30	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1697	0	0
T4	4701	20	0	0
T5	5293	0	0	0
T6	1488	3	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	18	0	0
T18	0	17	0	0
T21	1740	0	0	0
T28	0	11	0	0
T32	0	15	0	0
T45	0	47	0	0
T46	0	18	0	0
T47	0	96	0	0
T48	0	23	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	2183	0	0
T4	4701	12	0	0
T5	5293	0	0	0
T6	1488	8	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	30	0	0
T18	0	44	0	0
T21	1740	0	0	0
T28	0	2	0	0
T32	0	10	0	0
T45	0	106	0	0
T46	0	31	0	0
T47	0	211	0	0
T48	0	25	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1723	0	0
T4	4701	14	0	0
T5	5293	0	0	0
T6	1488	8	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	16	0	0
T18	0	26	0	0
T21	1740	0	0	0
T28	0	7	0	0
T32	0	6	0	0
T45	0	61	0	0
T46	0	30	0	0
T47	0	83	0	0
T48	0	31	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1969	0	0
T4	4701	8	0	0
T5	5293	0	0	0
T6	1488	0	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	11	0	0
T18	0	10	0	0
T21	1740	0	0	0
T28	0	3	0	0
T32	0	29	0	0
T45	0	97	0	0
T46	0	30	0	0
T47	0	147	0	0
T48	0	21	0	0
T49	0	62	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1664	0	0
T4	4701	16	0	0
T5	5293	0	0	0
T6	1488	4	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	12	0	0
T18	0	18	0	0
T21	1740	0	0	0
T28	0	8	0	0
T32	0	3	0	0
T45	0	49	0	0
T46	0	3	0	0
T47	0	127	0	0
T48	0	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1708	0	0
T4	4701	12	0	0
T5	5293	0	0	0
T6	1488	9	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	9	0	0
T18	0	27	0	0
T21	1740	0	0	0
T28	0	6	0	0
T32	0	17	0	0
T45	0	43	0	0
T46	0	27	0	0
T47	0	104	0	0
T48	0	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1650	0	0
T4	4701	47	0	0
T5	5293	0	0	0
T6	1488	5	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	11	0	0
T18	0	18	0	0
T21	1740	0	0	0
T28	0	6	0	0
T32	0	7	0	0
T45	0	59	0	0
T46	0	45	0	0
T47	0	94	0	0
T48	0	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1638	0	0
T4	4701	9	0	0
T5	5293	0	0	0
T6	1488	1	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	16	0	0
T18	0	22	0	0
T21	1740	0	0	0
T28	0	1	0	0
T32	0	16	0	0
T45	0	69	0	0
T46	0	21	0	0
T47	0	109	0	0
T48	0	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652987	1835	0	0
T4	4701	26	0	0
T5	5293	0	0	0
T6	1488	10	0	0
T9	9207	0	0	0
T10	4282	0	0	0
T11	932	0	0	0
T12	958	0	0	0
T13	4502	0	0	0
T14	4138	0	0	0
T17	0	10	0	0
T18	0	16	0	0
T21	1740	0	0	0
T28	0	8	0	0
T32	0	24	0	0
T45	0	70	0	0
T46	0	23	0	0
T47	0	159	0	0
T49	0	34	0	0