Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41069

1

T1

52

T2

278

T3

639

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33327	1			T1	60		T2	435		T3	150
values[0x0]	16173	1			T1	35		T2	138		T3	254
values[0x1]	16857	1			T1	26		T2	158		T3	301

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48713

1

T1

74

T2

433

T3

688

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	156	1			T6	1		T4	4		T14	1
valid_sources[0x01]	524	1			T2	4		T3	7		T6	2
valid_sources[0x02]	196	1			T3	5		T4	1		T14	2
valid_sources[0x03]	281	1			T3	1		T6	3		T4	7
valid_sources[0x04]	154	1			T3	3		T6	1		T4	9
valid_sources[0x05]	154	1			T2	2		T3	3		T4	6
valid_sources[0x06]	516	1			T3	4		T6	1		T4	9
valid_sources[0x07]	326	1			T3	1		T6	2		T4	4
valid_sources[0x08]	174	1			T2	1		T3	2		T6	4
valid_sources[0x09]	341	1			T3	4		T6	2		T4	4
valid_sources[0x0a]	235	1			T3	4		T4	6		T9	1
valid_sources[0x0b]	310	1			T2	3		T3	1		T6	3
valid_sources[0x0c]	143	1			T3	4		T4	3		T10	2
valid_sources[0x0d]	314	1			T3	4		T6	1		T4	5
valid_sources[0x0e]	225	1			T3	2		T8	3		T6	3
valid_sources[0x0f]	207	1			T2	5		T3	5		T6	2
valid_sources[0x10]	195	1			T3	5		T6	3		T4	9
valid_sources[0x11]	193	1			T3	1		T6	3		T4	8
valid_sources[0x12]	206	1			T3	1		T6	1		T4	3
valid_sources[0x13]	459	1			T2	2		T3	3		T6	2
valid_sources[0x14]	235	1			T6	1		T4	5		T55	1
valid_sources[0x15]	219	1			T2	7		T3	1		T6	2
valid_sources[0x16]	188	1			T3	6		T6	2		T4	13
valid_sources[0x17]	211	1			T2	5		T3	5		T6	1
valid_sources[0x18]	274	1			T2	12		T3	2		T6	1
valid_sources[0x19]	220	1			T2	3		T3	6		T6	1
valid_sources[0x1a]	258	1			T2	5		T3	1		T6	1
valid_sources[0x1b]	293	1			T3	4		T6	2		T4	7
valid_sources[0x1c]	235	1			T3	3		T4	4		T14	2
valid_sources[0x1d]	248	1			T3	4		T6	3		T4	6
valid_sources[0x1e]	188	1			T2	4		T3	3		T6	2
valid_sources[0x1f]	330	1			T2	10		T3	5		T6	2
valid_sources[0x20]	190	1			T4	5		T9	2		T55	1
valid_sources[0x21]	215	1			T3	4		T6	2		T4	8
valid_sources[0x22]	179	1			T2	2		T3	2		T4	4
valid_sources[0x23]	220	1			T2	5		T3	1		T6	1
valid_sources[0x24]	223	1			T3	2		T4	8		T14	2
valid_sources[0x25]	210	1			T2	1		T3	1		T6	6
valid_sources[0x26]	339	1			T2	11		T3	4		T6	1
valid_sources[0x27]	156	1			T2	14		T3	2		T6	6
valid_sources[0x28]	207	1			T2	9		T3	3		T6	1
valid_sources[0x29]	357	1			T2	4		T3	2		T6	5
valid_sources[0x2a]	220	1			T3	2		T4	4		T14	3
valid_sources[0x2b]	262	1			T2	6		T6	1		T4	5
valid_sources[0x2c]	247	1			T2	3		T3	2		T7	2
valid_sources[0x2d]	355	1			T2	3		T3	1		T7	2
valid_sources[0x2e]	358	1			T6	5		T4	5		T14	4
valid_sources[0x2f]	196	1			T3	2		T6	2		T4	5
valid_sources[0x30]	287	1			T3	6		T6	2		T4	8
valid_sources[0x31]	319	1			T3	2		T6	5		T4	5
valid_sources[0x32]	236	1			T3	6		T6	4		T4	5
valid_sources[0x33]	292	1			T2	1		T3	1		T6	2
valid_sources[0x34]	407	1			T2	12		T3	3		T6	1
valid_sources[0x35]	371	1			T3	2		T6	2		T4	1
valid_sources[0x36]	286	1			T3	4		T6	1		T4	10
valid_sources[0x37]	171	1			T3	2		T7	5		T6	1
valid_sources[0x38]	236	1			T3	2		T6	3		T4	11
valid_sources[0x39]	260	1			T2	1		T3	6		T7	2
valid_sources[0x3a]	330	1			T3	1		T7	4		T6	1
valid_sources[0x3b]	172	1			T3	9		T6	2		T4	3
valid_sources[0x3c]	145	1			T3	2		T6	1		T4	4
valid_sources[0x3d]	222	1			T2	16		T6	3		T4	6
valid_sources[0x3e]	196	1			T2	1		T6	2		T4	3
valid_sources[0x3f]	291	1			T2	6		T6	1		T4	6
valid_sources[0x40]	324	1			T2	1		T3	1		T6	5
valid_sources[0x41]	185	1			T2	3		T3	2		T6	4
valid_sources[0x42]	249	1			T3	3		T6	5		T4	4
valid_sources[0x43]	258	1			T3	1		T8	1		T6	2
valid_sources[0x44]	214	1			T8	5		T6	1		T4	9
valid_sources[0x45]	159	1			T3	1		T7	6		T6	3
valid_sources[0x46]	253	1			T4	9		T55	1		T15	4
valid_sources[0x47]	553	1			T3	4		T6	1		T4	3
valid_sources[0x48]	337	1			T3	1		T6	3		T4	8
valid_sources[0x49]	395	1			T2	2		T6	3		T4	3
valid_sources[0x4a]	187	1			T3	5		T4	4		T14	4
valid_sources[0x4b]	411	1			T2	16		T3	4		T6	4
valid_sources[0x4c]	277	1			T3	1		T6	1		T4	1
valid_sources[0x4d]	167	1			T3	3		T6	1		T4	4
valid_sources[0x4e]	221	1			T2	3		T3	1		T6	4
valid_sources[0x4f]	224	1			T3	9		T8	7		T6	3
valid_sources[0x50]	184	1			T2	7		T3	2		T4	7
valid_sources[0x51]	150	1			T2	4		T3	1		T6	2
valid_sources[0x52]	184	1			T3	4		T6	2		T4	3
valid_sources[0x53]	252	1			T3	2		T4	8		T14	5
valid_sources[0x54]	297	1			T3	4		T6	2		T4	8
valid_sources[0x55]	282	1			T2	16		T3	2		T6	2
valid_sources[0x56]	234	1			T2	14		T3	2		T6	3
valid_sources[0x57]	184	1			T2	6		T3	5		T6	3
valid_sources[0x58]	191	1			T2	9		T3	2		T6	1
valid_sources[0x59]	169	1			T3	1		T4	5		T14	1
valid_sources[0x5a]	178	1			T3	5		T6	2		T4	7
valid_sources[0x5b]	301	1			T2	6		T3	8		T6	2
valid_sources[0x5c]	199	1			T2	16		T3	2		T7	3
valid_sources[0x5d]	295	1			T2	3		T3	2		T4	7
valid_sources[0x5e]	212	1			T2	3		T3	10		T6	4
valid_sources[0x5f]	384	1			T2	1		T3	3		T6	1
valid_sources[0x60]	343	1			T2	8		T3	1		T6	3
valid_sources[0x61]	308	1			T3	1		T6	1		T4	6
valid_sources[0x62]	216	1			T3	2		T6	1		T4	11
valid_sources[0x63]	202	1			T2	1		T3	3		T7	3
valid_sources[0x64]	202	1			T2	8		T3	1		T6	6
valid_sources[0x65]	204	1			T2	5		T3	2		T6	3
valid_sources[0x66]	219	1			T3	3		T6	1		T4	3
valid_sources[0x67]	361	1			T3	3		T6	2		T4	6
valid_sources[0x68]	232	1			T3	2		T6	2		T4	4
valid_sources[0x69]	233	1			T6	3		T4	7		T14	1
valid_sources[0x6a]	215	1			T2	2		T4	8		T14	3
valid_sources[0x6b]	511	1			T2	1		T3	2		T6	1
valid_sources[0x6c]	320	1			T2	3		T3	1		T4	5
valid_sources[0x6d]	166	1			T2	2		T3	4		T4	3
valid_sources[0x6e]	157	1			T3	2		T6	1		T4	4
valid_sources[0x6f]	295	1			T2	1		T3	3		T6	2
valid_sources[0x70]	389	1			T3	1		T7	1		T8	1
valid_sources[0x71]	355	1			T3	2		T4	6		T5	51
valid_sources[0x72]	303	1			T2	4		T3	6		T6	4
valid_sources[0x73]	210	1			T3	5		T6	1		T4	4
valid_sources[0x74]	240	1			T2	1		T3	2		T6	1
valid_sources[0x75]	370	1			T2	15		T3	2		T6	1
valid_sources[0x76]	327	1			T3	1		T4	2		T14	7
valid_sources[0x77]	201	1			T3	3		T6	3		T4	5
valid_sources[0x78]	380	1			T3	1		T6	2		T4	5
valid_sources[0x79]	162	1			T3	5		T4	4		T14	1
valid_sources[0x7a]	229	1			T6	1		T4	5		T55	1
valid_sources[0x7b]	402	1			T3	3		T8	3		T6	2
valid_sources[0x7c]	313	1			T3	2		T6	2		T4	8
valid_sources[0x7d]	158	1			T3	1		T4	7		T14	6
valid_sources[0x7e]	316	1			T2	1		T3	3		T6	1
valid_sources[0x7f]	433	1			T2	2		T3	2		T4	5
valid_sources[0x80]	206	1			T3	6		T6	3		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14573

1

T1

13

T2

60

T3

150

values[0x0]

all_enables

biggest_size

13659

1

T1

20

T2

102

T3

251

values[0x1]

all_enables

biggest_size

12837

1

T1

19

T2

116

T3

238