Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	634475	0	0	0
ctrl_rd_A	634475	1430	0	0
host_fifo_config_rd_A	634475	1028	0	0
host_nack_handler_timeout_rd_A	634475	1132	0	0
host_timeout_ctrl_rd_A	634475	1114	0	0
intr_enable_rd_A	634475	2144	0	0
ovrd_rd_A	634475	1213	0	0
target_fifo_config_rd_A	634475	1091	0	0
target_id_rd_A	634475	1178	0	0
target_timeout_ctrl_rd_A	634475	1164	0	0
timeout_ctrl_rd_A	634475	1289	0	0
timing0_rd_A	634475	1066	0	0
timing1_rd_A	634475	1221	0	0
timing2_rd_A	634475	1054	0	0
timing3_rd_A	634475	1157	0	0
timing4_rd_A	634475	1033	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1430	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	30	0	0
T17	2758	13	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	13	0	0
T21	2257	0	0	0
T22	0	18	0	0
T26	0	43	0	0
T37	0	8	0	0
T55	2991	42	0	0
T56	2304	0	0	0
T60	0	23	0	0
T61	0	28	0	0
T62	0	6	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1028	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	15	0	0
T17	2758	8	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	21	0	0
T21	2257	0	0	0
T22	0	4	0	0
T26	0	47	0	0
T37	0	12	0	0
T55	2991	11	0	0
T56	2304	0	0	0
T60	0	44	0	0
T61	0	9	0	0
T62	0	1	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1132	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	9	0	0
T17	2758	11	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	17	0	0
T21	2257	0	0	0
T22	0	36	0	0
T26	0	57	0	0
T28	0	8	0	0
T37	0	12	0	0
T55	2991	5	0	0
T56	2304	0	0	0
T60	0	17	0	0
T61	0	53	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1114	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	31	0	0
T17	2758	3	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	13	0	0
T21	2257	0	0	0
T22	0	21	0	0
T26	0	31	0	0
T37	0	11	0	0
T55	2991	29	0	0
T56	2304	0	0	0
T60	0	16	0	0
T61	0	21	0	0
T62	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	2144	0	0
T11	1817	0	0	0
T13	2024	18	0	0
T15	3609	0	0	0
T16	9738	6	0	0
T17	2758	80	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	104	0	0
T21	2257	0	0	0
T22	0	41	0	0
T26	0	15	0	0
T34	0	10	0	0
T36	0	23	0	0
T55	2991	39	0	0
T56	2304	0	0	0
T63	0	5	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1213	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	30	0	0
T17	2758	16	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	16	0	0
T21	2257	0	0	0
T22	0	15	0	0
T26	0	43	0	0
T28	0	9	0	0
T37	0	8	0	0
T55	2991	25	0	0
T56	2304	0	0	0
T60	0	37	0	0
T61	0	31	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1091	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	17	0	0
T17	2758	3	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	11	0	0
T21	2257	0	0	0
T22	0	30	0	0
T26	0	16	0	0
T37	0	7	0	0
T55	2991	29	0	0
T56	2304	0	0	0
T60	0	25	0	0
T61	0	28	0	0
T62	0	7	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1178	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	6	0	0
T17	2758	29	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	27	0	0
T21	2257	0	0	0
T22	0	36	0	0
T26	0	18	0	0
T37	0	9	0	0
T55	2991	17	0	0
T56	2304	0	0	0
T60	0	39	0	0
T61	0	14	0	0
T62	0	5	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1164	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	23	0	0
T17	2758	21	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	29	0	0
T21	2257	0	0	0
T22	0	47	0	0
T26	0	45	0	0
T28	0	5	0	0
T37	0	3	0	0
T55	2991	2	0	0
T56	2304	0	0	0
T60	0	6	0	0
T61	0	16	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1289	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	30	0	0
T17	2758	3	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	27	0	0
T21	2257	0	0	0
T22	0	44	0	0
T26	0	49	0	0
T37	0	11	0	0
T55	2991	26	0	0
T56	2304	0	0	0
T60	0	35	0	0
T61	0	23	0	0
T62	0	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1066	0	0
T16	9738	18	0	0
T17	2758	1	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	3134	29	0	0
T22	0	14	0	0
T23	5960	0	0	0
T26	0	59	0	0
T28	0	6	0	0
T37	0	15	0	0
T59	1649	0	0	0
T60	0	22	0	0
T61	0	24	0	0
T62	0	6	0	0
T63	1714	0	0	0
T64	1060	0	0	0
T65	932	0	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1221	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	22	0	0
T17	2758	8	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	18	0	0
T21	2257	0	0	0
T22	0	25	0	0
T26	0	41	0	0
T37	0	18	0	0
T55	2991	4	0	0
T56	2304	0	0	0
T60	0	12	0	0
T61	0	34	0	0
T62	0	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1054	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	15	0	0
T17	2758	14	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	16	0	0
T21	2257	0	0	0
T22	0	11	0	0
T26	0	51	0	0
T37	0	8	0	0
T55	2991	15	0	0
T56	2304	0	0	0
T60	0	15	0	0
T61	0	17	0	0
T62	0	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1157	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	30	0	0
T17	2758	2	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	22	0	0
T21	2257	0	0	0
T22	0	21	0	0
T26	0	55	0	0
T37	0	9	0	0
T55	2991	15	0	0
T56	2304	0	0	0
T60	0	31	0	0
T61	0	32	0	0
T62	0	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634475	1033	0	0
T11	1817	0	0	0
T13	2024	0	0	0
T15	3609	0	0	0
T16	9738	21	0	0
T17	2758	15	0	0
T18	8357	0	0	0
T19	9264	0	0	0
T20	0	37	0	0
T21	2257	0	0	0
T22	0	46	0	0
T26	0	44	0	0
T37	0	6	0	0
T55	2991	19	0	0
T56	2304	0	0	0
T60	0	29	0	0
T61	0	13	0	0
T62	0	4	0	0