Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.19	85.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	85.19	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	8	19	70.37

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	8	19	70.37	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

183631

1

T7

1336

T15

12

T18

525

ack

274

1

T16

2

T25

2

T26

7

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	706	1			T7	5		T18	4		T23	8
high	38598	1			T7	302		T15	3		T18	119
med	69957	1			T7	531		T15	1		T18	195
sml	73928	1			T7	492		T15	8		T18	202
all_zero	716	1			T7	6		T18	5		T23	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92225

1

T7

667

T15

4

T18

268

auto[1]

91680

1

T7

669

T15

8

T18

257

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125195

1

T7

868

T15

12

T18

360

auto[1]

58710

1

T7

468

T18

165

T23

396

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179879

1

T7

1336

T15

6

T18

523

auto[1]

4026

1

T15

6

T18

2

T16

2

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176674

1

T7

1321

T15

6

T18

521

auto[1]

7231

1

T7

15

T15

6

T18

4

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177598

1

T7

1327

T15

6

T18

522

auto[1]

6307

1

T7

9

T15

6

T18

3

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92225

1

T7

667

T15

4

T18

268

auto[1]

91680

1

T7

669

T15

8

T18

257

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125195

1

T7

868

T15

12

T18

360

auto[1]

58710

1

T7

468

T18

165

T23

396

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179879

1

T7

1336

T15

6

T18

523

auto[1]

4026

1

T15

6

T18

2

T16

2

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176674

1

T7

1321

T15

6

T18

521

auto[1]

7231

1

T7

15

T15

6

T18

4

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177598

1

T7

1327

T15

6

T18

522

auto[1]

6307

1

T7

9

T15

6

T18

3

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	8	19	70.37	6
Automatically Generated Cross Bins	15	6	9	60.00	6
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T247

1

T248

1

T249

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T250

1

T251

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T26

1

T252

1

T253

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T30

2

T254

1

T255

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T26

1

T252

1

T249

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T256

1

T251

1

T257

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T26

1

T258

1

T259

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

9

1

T260

2

T251

1

T261

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T26

1

T252

1

T262

2

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	56409	1			T7	413		T18	182		T23	380
write_address_byte	7231	1			T7	15		T15	6		T18	4
read_with_ack	891	1			T18	1		T16	1		T25	2
read_with_nack	3135	1			T15	6		T18	1		T16	1
stop_byte	6307	1			T7	9		T15	6		T18	3
write_address_byte_nak	7136	1			T7	15		T15	6		T18	4
data_byte_nack	183631	1			T7	1336		T15	12		T18	525
stop_byte_nack	6257	1			T7	9		T15	6		T18	3
nakok_byte_nack	91537	1			T7	669		T15	8		T18	257
nakok_addr_byte_nack	3565	1			T7	5		T15	4		T18	1