Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28068968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8124992

1

T1

13

T2

29

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35302283	1			T1	15		T2	4		T3	14
values[0x0]	443152	1			T1	10		T2	23		T3	9
values[0x1]	448525	1			T1	6		T2	26		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19757000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16436960

1

T1

17

T2

33

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	134429	1			T6	1		T7	110		T8	30
valid_sources[0x01]	130949	1			T4	5		T6	6		T7	98
valid_sources[0x02]	129600	1			T7	106		T8	36		T9	43
valid_sources[0x03]	132893	1			T7	116		T8	41		T9	49
valid_sources[0x04]	137702	1			T7	107		T8	22		T9	56
valid_sources[0x05]	147035	1			T1	1		T6	1		T7	110
valid_sources[0x06]	140576	1			T7	141		T8	43		T9	54
valid_sources[0x07]	137141	1			T4	1		T7	93		T8	28
valid_sources[0x08]	126500	1			T6	2		T7	132		T8	37
valid_sources[0x09]	148687	1			T2	2		T6	1		T7	96
valid_sources[0x0a]	133351	1			T7	106		T8	34		T9	47
valid_sources[0x0b]	127218	1			T7	112		T8	29		T9	47
valid_sources[0x0c]	138704	1			T6	5		T7	105		T8	32
valid_sources[0x0d]	142349	1			T7	119		T8	30		T9	51
valid_sources[0x0e]	141394	1			T7	100		T8	23		T9	35
valid_sources[0x0f]	141573	1			T6	1		T7	121		T8	26
valid_sources[0x10]	134229	1			T7	86		T8	18		T9	51
valid_sources[0x11]	138717	1			T1	1		T7	95		T8	28
valid_sources[0x12]	147323	1			T7	100		T8	36		T9	44
valid_sources[0x13]	164979	1			T7	98		T8	23		T9	59
valid_sources[0x14]	138678	1			T1	1		T4	1		T7	107
valid_sources[0x15]	152675	1			T3	2		T7	122		T8	28
valid_sources[0x16]	132878	1			T7	111		T8	29		T9	61
valid_sources[0x17]	132678	1			T7	103		T8	38		T9	63
valid_sources[0x18]	141191	1			T7	98		T8	41		T9	70
valid_sources[0x19]	131217	1			T7	146		T8	38		T9	46
valid_sources[0x1a]	136825	1			T7	113		T8	32		T9	49
valid_sources[0x1b]	139572	1			T6	1		T7	108		T8	27
valid_sources[0x1c]	135287	1			T6	1		T7	119		T8	30
valid_sources[0x1d]	140507	1			T7	114		T8	21		T9	65
valid_sources[0x1e]	131879	1			T4	1		T6	4		T7	115
valid_sources[0x1f]	154301	1			T7	94		T8	38		T9	65
valid_sources[0x20]	152034	1			T7	113		T8	55		T9	52
valid_sources[0x21]	148332	1			T7	114		T8	43		T9	56
valid_sources[0x22]	354829	1			T7	96		T8	31		T9	56
valid_sources[0x23]	141798	1			T5	4		T6	2		T7	112
valid_sources[0x24]	126685	1			T4	2		T7	121		T8	37
valid_sources[0x25]	143652	1			T6	2		T7	137		T8	44
valid_sources[0x26]	158026	1			T6	1		T7	102		T8	34
valid_sources[0x27]	137717	1			T7	164		T8	48		T9	52
valid_sources[0x28]	148959	1			T7	104		T8	39		T9	44
valid_sources[0x29]	132418	1			T6	2		T7	122		T8	51
valid_sources[0x2a]	150813	1			T6	1		T7	113		T8	24
valid_sources[0x2b]	133774	1			T1	1		T6	3		T7	125
valid_sources[0x2c]	133269	1			T4	2		T7	90		T8	34
valid_sources[0x2d]	136306	1			T4	4		T7	125		T8	41
valid_sources[0x2e]	139098	1			T6	1		T7	120		T8	42
valid_sources[0x2f]	142895	1			T7	151		T8	31		T9	46
valid_sources[0x30]	138048	1			T6	1		T7	134		T8	29
valid_sources[0x31]	133446	1			T7	99		T8	44		T9	54
valid_sources[0x32]	153269	1			T6	1		T7	113		T8	24
valid_sources[0x33]	149082	1			T6	1		T7	97		T8	38
valid_sources[0x34]	132919	1			T7	86		T8	31		T9	56
valid_sources[0x35]	137325	1			T4	2		T7	138		T8	27
valid_sources[0x36]	148797	1			T7	91		T8	31		T9	51
valid_sources[0x37]	138919	1			T4	6		T7	126		T8	32
valid_sources[0x38]	151224	1			T3	1		T6	1		T7	107
valid_sources[0x39]	145197	1			T7	86		T8	24		T9	68
valid_sources[0x3a]	130985	1			T7	103		T8	31		T9	53
valid_sources[0x3b]	144734	1			T7	102		T8	27		T9	47
valid_sources[0x3c]	137466	1			T7	76		T8	25		T9	42
valid_sources[0x3d]	133282	1			T7	100		T8	41		T9	50
valid_sources[0x3e]	136195	1			T6	4		T7	114		T8	26
valid_sources[0x3f]	147835	1			T7	108		T8	33		T9	55
valid_sources[0x40]	130788	1			T4	6		T7	105		T8	28
valid_sources[0x41]	134845	1			T7	110		T8	37		T9	57
valid_sources[0x42]	133646	1			T7	123		T8	32		T9	45
valid_sources[0x43]	144803	1			T7	112		T8	37		T9	53
valid_sources[0x44]	210582	1			T4	2		T7	111		T8	31
valid_sources[0x45]	137520	1			T7	130		T8	34		T9	62
valid_sources[0x46]	155694	1			T7	94		T8	30		T9	43
valid_sources[0x47]	146810	1			T7	126		T8	33		T9	44
valid_sources[0x48]	162731	1			T7	109		T8	30		T9	57
valid_sources[0x49]	128375	1			T6	1		T7	122		T8	32
valid_sources[0x4a]	138574	1			T7	129		T8	35		T9	44
valid_sources[0x4b]	152790	1			T7	117		T8	38		T9	54
valid_sources[0x4c]	151950	1			T7	113		T8	33		T9	56
valid_sources[0x4d]	134262	1			T6	1		T7	111		T8	34
valid_sources[0x4e]	122530	1			T7	129		T8	44		T9	52
valid_sources[0x4f]	130706	1			T7	107		T8	41		T9	44
valid_sources[0x50]	134142	1			T1	2		T7	95		T8	47
valid_sources[0x51]	136111	1			T7	110		T8	36		T9	45
valid_sources[0x52]	140738	1			T7	94		T8	39		T9	61
valid_sources[0x53]	129552	1			T6	1		T7	117		T8	34
valid_sources[0x54]	128215	1			T7	129		T8	34		T9	61
valid_sources[0x55]	124798	1			T4	4		T7	123		T8	27
valid_sources[0x56]	133218	1			T6	1		T7	115		T8	52
valid_sources[0x57]	147633	1			T6	2		T7	101		T8	33
valid_sources[0x58]	135464	1			T7	118		T8	31		T9	38
valid_sources[0x59]	146855	1			T7	111		T8	33		T9	44
valid_sources[0x5a]	135919	1			T7	114		T8	24		T9	55
valid_sources[0x5b]	149874	1			T3	2		T7	82		T8	29
valid_sources[0x5c]	147397	1			T4	2		T7	110		T8	30
valid_sources[0x5d]	133317	1			T7	123		T8	25		T9	65
valid_sources[0x5e]	145195	1			T7	111		T8	28		T9	42
valid_sources[0x5f]	136263	1			T3	1		T7	100		T8	32
valid_sources[0x60]	126896	1			T2	24		T3	1		T6	2
valid_sources[0x61]	143678	1			T7	118		T8	28		T9	55
valid_sources[0x62]	158222	1			T4	1		T7	119		T8	45
valid_sources[0x63]	150292	1			T4	1		T7	122		T8	26
valid_sources[0x64]	144506	1			T1	1		T7	167		T8	30
valid_sources[0x65]	139969	1			T7	117		T8	36		T9	40
valid_sources[0x66]	130647	1			T1	1		T6	1		T7	110
valid_sources[0x67]	174112	1			T6	4		T7	113		T8	19
valid_sources[0x68]	136206	1			T5	25		T6	1		T7	105
valid_sources[0x69]	143395	1			T7	128		T8	33		T9	57
valid_sources[0x6a]	262658	1			T7	89		T8	22		T9	42
valid_sources[0x6b]	146198	1			T4	3		T6	2		T7	136
valid_sources[0x6c]	130122	1			T4	4		T7	119		T8	29
valid_sources[0x6d]	149930	1			T3	1		T6	1		T7	113
valid_sources[0x6e]	136645	1			T1	1		T7	100		T8	44
valid_sources[0x6f]	125275	1			T7	124		T8	25		T9	47
valid_sources[0x70]	142491	1			T4	1		T6	1		T7	136
valid_sources[0x71]	139871	1			T5	22		T7	99		T8	36
valid_sources[0x72]	124842	1			T7	96		T8	24		T9	46
valid_sources[0x73]	134572	1			T7	94		T8	27		T9	64
valid_sources[0x74]	126002	1			T1	1		T3	1		T6	1
valid_sources[0x75]	143560	1			T4	1		T6	1		T7	105
valid_sources[0x76]	139736	1			T4	3		T6	1		T7	126
valid_sources[0x77]	146064	1			T7	95		T8	28		T9	56
valid_sources[0x78]	154446	1			T6	1		T7	100		T8	33
valid_sources[0x79]	132386	1			T6	1		T7	129		T8	32
valid_sources[0x7a]	159845	1			T5	28		T7	120		T8	37
valid_sources[0x7b]	143354	1			T4	5		T7	97		T8	34
valid_sources[0x7c]	140745	1			T1	1		T4	2		T7	95
valid_sources[0x7d]	139647	1			T7	121		T8	53		T9	64
valid_sources[0x7e]	125594	1			T4	7		T7	93		T8	28
valid_sources[0x7f]	126919	1			T7	96		T8	33		T9	48
valid_sources[0x80]	137816	1			T7	94		T8	25		T9	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7695613

1

T1

8

T2

1

T3

9

values[0x0]

all_enables

biggest_size

248904

1

T1

4

T2

14

T3

2

values[0x1]

all_enables

biggest_size

180475

1

T1

1

T2

14

T4

9