Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf	91.67	100.00	66.67			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	100.00	72.73			90.91	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	88.21	100.00	80.00			84.62

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.63	100.00	74.51			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	400146036	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	400146036	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	400146036	0	0
T2	103960	50787	0	0
T3	5394	0	0	0
T4	26840	10519	0	0
T5	28038	10638	0	0
T6	25070	699	0	0
T7	1020248	252235	0	0
T8	996292	211637	0	0
T9	417824	3042	0	0
T10	833504	193894	0	0
T14	0	806	0	0
T15	161223	148729	0	0
T16	0	39702	0	0
T17	0	7	0	0
T18	575906	575264	0	0
T23	238160	237499	0	0
T24	0	306570	0	0
T44	0	42898	0	0
T45	0	243981	0	0
T47	0	4955	0	0
T48	202992	50574	0	0
T49	28716	5119	0	0
T50	22132	5563	0	0
T51	1920678	0	0	0
T52	38362	0	0	0
T53	3468	0	0	0
T56	52467	0	0	0
T75	13600	0	0	0
T79	1551	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18056	17256	0	0
T2	415840	415296	0	0
T3	21576	20904	0	0
T4	107360	106584	0	0
T5	112152	111456	0	0
T6	100280	99512	0	0
T7	2040496	2039928	0	0
T8	1992584	1992520	0	0
T9	835648	835040	0	0
T10	1667008	1666544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18056	17256	0	0
T2	415840	415296	0	0
T3	21576	20904	0	0
T4	107360	106584	0	0
T5	112152	111456	0	0
T6	100280	99512	0	0
T7	2040496	2039928	0	0
T8	1992584	1992520	0	0
T9	835648	835040	0	0
T10	1667008	1666544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18056	17256	0	0
T2	415840	415296	0	0
T3	21576	20904	0	0
T4	107360	106584	0	0
T5	112152	111456	0	0
T6	100280	99512	0	0
T7	2040496	2039928	0	0
T8	1992584	1992520	0	0
T9	835648	835040	0	0
T10	1667008	1666544	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	400146036	0	0
T2	103960	50787	0	0
T3	5394	0	0	0
T4	26840	10519	0	0
T5	28038	10638	0	0
T6	25070	699	0	0
T7	1020248	252235	0	0
T8	996292	211637	0	0
T9	417824	3042	0	0
T10	833504	193894	0	0
T14	0	806	0	0
T15	161223	148729	0	0
T16	0	39702	0	0
T17	0	7	0	0
T18	575906	575264	0	0
T23	238160	237499	0	0
T24	0	306570	0	0
T44	0	42898	0	0
T45	0	243981	0	0
T47	0	4955	0	0
T48	202992	50574	0	0
T49	28716	5119	0	0
T50	22132	5563	0	0
T51	1920678	0	0	0
T52	38362	0	0	0
T53	3468	0	0	0
T56	52467	0	0	0
T75	13600	0	0	0
T79	1551	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	16	66.67
Logical	24	16	66.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T18,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T18,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T18,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T18,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T18,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T18,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T15,T18,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T15,T18,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	220788	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	220788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	220788	0	0
T15	161223	768	0	0
T16	0	181	0	0
T17	0	7	0	0
T18	575906	512	0	0
T19	0	768	0	0
T23	238160	0	0	0
T24	310270	0	0	0
T25	0	91	0	0
T26	0	99	0	0
T36	0	1152	0	0
T47	7039	0	0	0
T56	52467	0	0	0
T60	527239	0	0	0
T75	13600	0	0	0
T76	14801	0	0	0
T79	1551	0	0	0
T82	0	1280	0	0
T160	0	597	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	220788	0	0
T15	161223	768	0	0
T16	0	181	0	0
T17	0	7	0	0
T18	575906	512	0	0
T19	0	768	0	0
T23	238160	0	0	0
T24	310270	0	0	0
T25	0	91	0	0
T26	0	99	0	0
T36	0	1152	0	0
T47	7039	0	0	0
T56	52467	0	0	0
T60	527239	0	0	0
T75	13600	0	0	0
T76	14801	0	0	0
T79	1551	0	0	0
T82	0	1280	0	0
T160	0	597	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T14,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T23,T24
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T15

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T14,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T23,T24
1	0	Covered	T7,T14,T15
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T14,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T14,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	212562	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	212562	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	212562	0	0
T7	255062	1339	0	0
T8	249073	0	0	0
T9	104456	0	0	0
T10	208376	0	0	0
T14	0	21	0	0
T15	0	24	0	0
T16	0	21	0	0
T18	0	527	0	0
T23	0	1217	0	0
T24	0	1688	0	0
T44	0	197	0	0
T45	0	1141	0	0
T47	0	2	0	0
T48	50748	0	0	0
T49	14358	0	0	0
T50	11066	0	0	0
T51	960339	0	0	0
T52	19181	0	0	0
T53	1734	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	212562	0	0
T7	255062	1339	0	0
T8	249073	0	0	0
T9	104456	0	0	0
T10	208376	0	0	0
T14	0	21	0	0
T15	0	24	0	0
T16	0	21	0	0
T18	0	527	0	0
T23	0	1217	0	0
T24	0	1688	0	0
T44	0	197	0	0
T45	0	1141	0	0
T47	0	2	0	0
T48	50748	0	0	0
T49	14358	0	0	0
T50	11066	0	0	0
T51	960339	0	0	0
T52	19181	0	0	0
T53	1734	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T8,T80
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	166154	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	166154	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	166154	0	0
T4	13420	64	0	0
T5	14019	51	0	0
T6	12535	74	0	0
T7	255062	0	0	0
T8	249073	1327	0	0
T9	104456	481	0	0
T10	208376	18	0	0
T48	50748	0	0	0
T49	14358	92	0	0
T50	11066	80	0	0
T52	0	64	0	0
T75	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	166154	0	0
T4	13420	64	0	0
T5	14019	51	0	0
T6	12535	74	0	0
T7	255062	0	0	0
T8	249073	1327	0	0
T9	104456	481	0	0
T10	208376	18	0	0
T48	50748	0	0	0
T49	14358	92	0	0
T50	11066	80	0	0
T52	0	64	0	0
T75	0	56	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T58,T61,T161
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T58,T61,T161
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	319365	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	319365	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	319365	0	0
T2	51980	268	0	0
T3	2697	0	0	0
T4	13420	2	0	0
T5	14019	2	0	0
T6	12535	2	0	0
T7	255062	0	0	0
T8	249073	2840	0	0
T9	104456	102	0	0
T10	208376	1221	0	0
T48	50748	260	0	0
T49	0	19	0	0
T50	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	319365	0	0
T2	51980	268	0	0
T3	2697	0	0	0
T4	13420	2	0	0
T5	14019	2	0	0
T6	12535	2	0	0
T7	255062	0	0	0
T8	249073	2840	0	0
T9	104456	102	0	0
T10	208376	1221	0	0
T48	50748	260	0	0
T49	0	19	0	0
T50	0	17	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T14,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T14,T15

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T15
1	0	Covered	T7,T14,T15
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T14,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T14,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	122328056	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	122328056	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	122328056	0	0
T7	255062	250896	0	0
T8	249073	0	0	0
T9	104456	0	0	0
T10	208376	0	0	0
T14	0	785	0	0
T15	0	147937	0	0
T16	0	39500	0	0
T18	0	574225	0	0
T23	0	236282	0	0
T24	0	304882	0	0
T44	0	42701	0	0
T45	0	242840	0	0
T47	0	4953	0	0
T48	50748	0	0	0
T49	14358	0	0	0
T50	11066	0	0	0
T51	960339	0	0	0
T52	19181	0	0	0
T53	1734	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	122328056	0	0
T7	255062	250896	0	0
T8	249073	0	0	0
T9	104456	0	0	0
T10	208376	0	0	0
T14	0	785	0	0
T15	0	147937	0	0
T16	0	39500	0	0
T18	0	574225	0	0
T23	0	236282	0	0
T24	0	304882	0	0
T44	0	42701	0	0
T45	0	242840	0	0
T47	0	4953	0	0
T48	50748	0	0	0
T49	14358	0	0	0
T50	11066	0	0	0
T51	960339	0	0	0
T52	19181	0	0	0
T53	1734	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T36,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T18,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T18,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T15,T18,T16
1	1	0	Not Covered
1	1	1	Covered	T15,T18,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T18,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T36,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T18,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T16
1	0	Covered	T15,T18,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T15,T18,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T15,T18,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	28583842	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	28583842	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	28583842	0	0
T15	161223	154049	0	0
T16	0	1194	0	0
T17	0	234	0	0
T18	575906	3411	0	0
T19	0	16523	0	0
T23	238160	0	0	0
T24	310270	0	0	0
T25	0	2559	0	0
T26	0	3034	0	0
T36	0	225121	0	0
T47	7039	0	0	0
T56	52467	0	0	0
T60	527239	0	0	0
T75	13600	0	0	0
T76	14801	0	0	0
T79	1551	0	0	0
T82	0	267098	0	0
T160	0	3990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	28583842	0	0
T15	161223	154049	0	0
T16	0	1194	0	0
T17	0	234	0	0
T18	575906	3411	0	0
T19	0	16523	0	0
T23	238160	0	0	0
T24	310270	0	0	0
T25	0	2559	0	0
T26	0	3034	0	0
T36	0	225121	0	0
T47	7039	0	0	0
T56	52467	0	0	0
T60	527239	0	0	0
T75	13600	0	0	0
T76	14801	0	0	0
T79	1551	0	0	0
T82	0	267098	0	0
T160	0	3990	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	34095643	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	34095643	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	34095643	0	0
T4	13420	11898	0	0
T5	14019	11825	0	0
T6	12535	6595	0	0
T7	255062	0	0	0
T8	249073	274401	0	0
T9	104456	93684	0	0
T10	208376	4524	0	0
T48	50748	0	0	0
T49	14358	8204	0	0
T50	11066	8635	0	0
T52	0	9301	0	0
T75	0	12158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	34095643	0	0
T4	13420	11898	0	0
T5	14019	11825	0	0
T6	12535	6595	0	0
T7	255062	0	0	0
T8	249073	274401	0	0
T9	104456	93684	0	0
T10	208376	4524	0	0
T48	50748	0	0	0
T49	14358	8204	0	0
T50	11066	8635	0	0
T52	0	9301	0	0
T75	0	12158	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T162,T120,T163
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377458188	214219626	0	0
DepthKnown_A	377458188	377280912	0	0
RvalidKnown_A	377458188	377280912	0	0
WreadyKnown_A	377458188	377280912	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	377458188	214219626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	214219626	0	0
T2	51980	50519	0	0
T3	2697	0	0	0
T4	13420	10517	0	0
T5	14019	10636	0	0
T6	12535	697	0	0
T7	255062	0	0	0
T8	249073	208797	0	0
T9	104456	2940	0	0
T10	208376	192673	0	0
T48	50748	50314	0	0
T49	0	5100	0	0
T50	0	5546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	377280912	0	0
T1	2257	2157	0	0
T2	51980	51912	0	0
T3	2697	2613	0	0
T4	13420	13323	0	0
T5	14019	13932	0	0
T6	12535	12439	0	0
T7	255062	254991	0	0
T8	249073	249065	0	0
T9	104456	104380	0	0
T10	208376	208318	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	377458188	214219626	0	0
T2	51980	50519	0	0
T3	2697	0	0	0
T4	13420	10517	0	0
T5	14019	10636	0	0
T6	12535	697	0	0
T7	255062	0	0	0
T8	249073	208797	0	0
T9	104456	2940	0	0
T10	208376	192673	0	0
T48	50748	50314	0	0
T49	0	5100	0	0
T50	0	5546	0	0