Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	378129761	0	0	0
ctrl_rd_A	378129761	2979	0	0
host_fifo_config_rd_A	378129761	4192	0	0
host_nack_handler_timeout_rd_A	378129761	1677	0	0
host_timeout_ctrl_rd_A	378129761	1618	0	0
intr_enable_rd_A	378129761	4435	0	0
ovrd_rd_A	378129761	2513	0	0
target_fifo_config_rd_A	378129761	1968	0	0
target_id_rd_A	378129761	2123	0	0
target_timeout_ctrl_rd_A	378129761	1756	0	0
timeout_ctrl_rd_A	378129761	2001	0	0
timing0_rd_A	378129761	1738	0	0
timing1_rd_A	378129761	1853	0	0
timing2_rd_A	378129761	1845	0	0
timing3_rd_A	378129761	1686	0	0
timing4_rd_A	378129761	1774	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	2979	0	0
T99	13905	27	0	0
T100	3505	48	0	0
T101	2447	44	0	0
T102	2655	43	0	0
T103	2905	10	0	0
T104	2127	26	0	0
T105	12970	35	0	0
T106	8503	10	0	0
T107	7532	37	0	0
T108	6499	16	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	4192	0	0
T31	491132	203	0	0
T40	12670	0	0	0
T63	38653	0	0	0
T84	0	149	0	0
T109	0	317	0	0
T110	0	241	0	0
T111	0	231	0	0
T112	0	94	0	0
T113	0	75	0	0
T114	0	210	0	0
T115	0	66	0	0
T116	0	93	0	0
T117	117098	0	0	0
T118	48497	0	0	0
T119	329518	0	0	0
T120	23237	0	0	0
T121	191648	0	0	0
T122	100765	0	0	0
T123	15670	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1677	0	0
T99	13905	18	0	0
T100	3505	25	0	0
T101	2447	13	0	0
T102	2655	24	0	0
T103	2905	19	0	0
T105	12970	17	0	0
T106	8503	7	0	0
T107	7532	24	0	0
T108	6499	21	0	0
T124	8537	71	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1618	0	0
T99	13905	55	0	0
T100	3505	30	0	0
T101	2447	5	0	0
T102	2655	17	0	0
T103	2905	17	0	0
T105	12970	18	0	0
T106	8503	20	0	0
T107	7532	29	0	0
T108	6499	33	0	0
T124	8537	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	4435	0	0
T21	430386	36	0	0
T99	0	15	0	0
T100	0	42	0	0
T101	0	58	0	0
T102	0	7	0	0
T103	0	14	0	0
T109	0	19	0	0
T125	0	13	0	0
T126	0	1	0	0
T127	0	3	0	0
T128	165968	0	0	0
T129	20627	0	0	0
T130	60666	0	0	0
T131	6434	0	0	0
T132	12856	0	0	0
T133	16929	0	0	0
T134	30844	0	0	0
T135	101072	0	0	0
T136	105052	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	2513	0	0
T1	2257	39	0	0
T2	51980	0	0	0
T3	2697	0	0	0
T4	13420	0	0	0
T5	14019	0	0	0
T6	12535	0	0	0
T7	255062	0	0	0
T8	249073	0	0	0
T9	104456	0	0	0
T10	208376	0	0	0
T137	0	43	0	0
T138	0	46	0	0
T139	0	44	0	0
T140	0	32	0	0
T141	0	18	0	0
T142	0	61	0	0
T143	0	69	0	0
T144	0	29	0	0
T145	0	71	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1968	0	0
T99	13905	34	0	0
T100	3505	18	0	0
T101	2447	11	0	0
T102	2655	13	0	0
T103	2905	15	0	0
T104	2127	3	0	0
T105	12970	33	0	0
T106	8503	20	0	0
T107	7532	23	0	0
T108	6499	32	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	2123	0	0
T99	13905	14	0	0
T100	3505	12	0	0
T101	2447	8	0	0
T102	2655	37	0	0
T103	2905	12	0	0
T104	2127	5	0	0
T105	12970	44	0	0
T106	8503	11	0	0
T108	6499	21	0	0
T124	8537	111	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1756	0	0
T99	13905	63	0	0
T100	3505	9	0	0
T101	2447	16	0	0
T102	2655	28	0	0
T103	2905	10	0	0
T105	12970	26	0	0
T106	8503	8	0	0
T107	7532	14	0	0
T108	6499	30	0	0
T124	8537	61	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	2001	0	0
T99	13905	24	0	0
T100	3505	17	0	0
T101	2447	23	0	0
T102	2655	43	0	0
T103	2905	27	0	0
T105	12970	20	0	0
T106	8503	1	0	0
T107	7532	36	0	0
T108	6499	10	0	0
T124	8537	51	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1738	0	0
T99	13905	28	0	0
T100	3505	23	0	0
T101	2447	12	0	0
T102	2655	14	0	0
T103	2905	31	0	0
T105	12970	37	0	0
T106	8503	16	0	0
T107	7532	20	0	0
T108	6499	17	0	0
T124	8537	50	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1853	0	0
T99	13905	24	0	0
T100	3505	4	0	0
T101	2447	13	0	0
T102	2655	31	0	0
T103	2905	22	0	0
T104	2127	8	0	0
T105	12970	48	0	0
T106	8503	14	0	0
T107	7532	27	0	0
T108	6499	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1845	0	0
T99	13905	29	0	0
T101	2447	7	0	0
T102	2655	26	0	0
T103	2905	20	0	0
T105	12970	51	0	0
T106	8503	17	0	0
T107	7532	13	0	0
T108	6499	19	0	0
T124	8537	85	0	0
T146	6808	50	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1686	0	0
T99	13905	46	0	0
T100	3505	20	0	0
T101	2447	18	0	0
T102	2655	16	0	0
T103	2905	20	0	0
T104	2127	8	0	0
T105	12970	43	0	0
T106	8503	16	0	0
T107	7532	21	0	0
T108	6499	18	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378129761	1774	0	0
T99	13905	22	0	0
T100	3505	3	0	0
T101	2447	12	0	0
T102	2655	18	0	0
T103	2905	21	0	0
T105	12970	71	0	0
T106	8503	14	0	0
T107	7532	12	0	0
T108	6499	21	0	0
T124	8537	67	0	0